MCQOPTIONS
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MCQOPTIONS
This section includes 242 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
Which of the following method is not used to remove the race around condition in a flip flop? |
| A. | using level triggered flip flop |
| B. | using master slave flip flop |
| C. | using edge triggered flip flop |
| D. | all of the above are used to remove the race around |
| Answer» B. using master slave flip flop | |
| 102. |
The process used for implementation of sequential logic in VHDL is called              process. |
| A. | sequential process |
| B. | combinational process |
| C. | clocked process |
| D. | unclocked process |
| Answer» D. unclocked process | |
| 103. |
A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as |
| A. | switching condition |
| B. | master slave condition |
| C. | race around condition |
| D. | edge triggered condition |
| Answer» D. edge triggered condition | |
| 104. |
Why do we need to define clock signal in the sensitivity list of the process? |
| A. | to trigger the statement as soon as there is some event on clock |
| B. | to trigger the clock signal as soon as there is some event on input |
| C. | to trigger the clock signal as soon as there is some event on output |
| D. | to trigger the statement as soon as there is some event on input |
| Answer» B. to trigger the clock signal as soon as there is some event on input | |
| 105. |
The following timing diagram shows              flip flop. |
| A. | t flip-flop |
| B. | d flip-flop |
| C. | sr flip-flop |
| D. | jk flip-flop |
| Answer» C. sr flip-flop | |
| 106. |
A sequential logic can’t be executed by concurrent statements only. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 107. |
Which of the following sequential circuit doesn’t need a clock signal? |
| A. | flip flop |
| B. | asynchronous counter |
| C. | shift register |
| D. | latch |
| Answer» E. | |
| 108. |
A decimal counter has              states. |
| A. | 5 |
| B. | 10 |
| C. | 15 |
| D. | 20 |
| Answer» C. 15 | |
| 109. |
4 COUNTERS |
| A. | 0 to 2n |
| B. | 0 to 2n + 1 |
| C. | 0 to 2n – 1 d) 0 to 2n+1/2 |
| Answer» D. | |
| 110. |
The NAND latch works when both inputs are |
| A. | 1 |
| B. | 0 |
| C. | inverted |
| D. | don’t cares |
| Answer» B. 0 | |
| 111. |
The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? |
| A. | because of inverted outputs |
| B. | because of triggering functionality |
| C. | because of cross-coupled connection |
| D. | because of inverted outputs & triggering functionality |
| Answer» D. because of inverted outputs & triggering functionality | |
| 112. |
A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates? |
| A. | and or or gates |
| B. | xor or xnor gates |
| C. | nor or nand gates |
| D. | and or nor gates |
| Answer» D. and or nor gates | |
| 113. |
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? |
| A. | low input voltages |
| B. | synchronous operation |
| C. | gate impedance |
| D. | cross coupling |
| Answer» E. | |
| 114. |
A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively? |
| A. | binary, octal |
| B. | octal, binary |
| C. | hexadecimal, binary |
| D. | binary, hexadecimal |
| Answer» D. binary, hexadecimal | |
| 115. |
For using a process to implement a combinational circuit, which signals should be in the sensitivity list? |
| A. | inputs of the circuit |
| B. | outputs of the circuit |
| C. | both of the inputs and outputs |
| D. | no signal should be in the sensitivity list |
| Answer» B. outputs of the circuit | |
| 116. |
In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same? |
| A. | with-select |
| B. | with-select-when |
| C. | if-else |
| D. | case |
| Answer» C. if-else | |
| 117. |
A stepper motor HDL application must include |
| A. | sequencers and multiplexers |
| B. | types and bits |
| C. | counters and decoders |
| D. | variables and processes |
| Answer» D. variables and processes | |
| 118. |
11 HDL MODELS OF COMBINATIONAL CIRCUITS |
| A. | true |
| B. | false |
| Answer» C. | |
| 119. |
A major block which is not a part of an HDL frequency counter |
| A. | timing and control unit |
| B. | decoder/display |
| C. | display register |
| D. | bit shifter |
| Answer» E. | |
| 120. |
In the keypad application, the preset state of the ring counter define |
| A. | the nanding of the columns |
| B. | the nanding of the rows |
| C. | the proper output of the column encoder |
| D. | the proper output of the row encoder |
| Answer» E. | |
| 121. |
What does the data signal do in the keypad application? |
| A. | the row and column encoded data |
| B. | the ring encoded data |
| C. | the freeze locator data |
| D. | the ring counter data |
| Answer» B. the ring encoded data | |
| 122. |
A step which should be followed in project management is known as |
| A. | overall definition |
| B. | system documentation |
| C. | synthesis and testing |
| D. | system integration |
| Answer» C. synthesis and testing | |
| 123. |
When a key is pressed, what does the ring counter in the HDL keypad application do? |
| A. | count to find the row |
| B. | freeze |
| C. | count to find the column |
| D. | start the d flip-flop |
| Answer» B. freeze | |
| 124. |
In a digital clock application, the basic frequency must be divided down as |
| A. | 1 hz |
| B. | 60 hz |
| C. | 100 hz |
| D. | 1000 hz |
| Answer» B. 60 hz | |
| 125. |
In an HDL application of a stepper motor, what is done next after an up/down counter is built? |
| A. | build the sequencer |
| B. | test it on a simulator |
| C. | test the decoder |
| D. | design an intermediate integer variable |
| Answer» C. test the decoder | |
| 126. |
The output frequency related to the sampling interval of a frequency counter as |
| A. | directly with the sampling interval |
| B. | inversely with the sampling interval |
| C. | more precision with longer sampling interval |
| D. | less precision with longer sampling interval |
| Answer» D. less precision with longer sampling interval | |
| 127. |
At high frequencies when the sampling interval is too long in a frequency counter |
| A. | the counter works fine |
| B. | the counter undercounts the frequency |
| C. | the measurement is less precise |
| D. | the counter overflows |
| Answer» E. | |
| 128. |
The use of VHDL can be done in            ways. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 129. |
VHDL is being used for |
| A. | documentation |
| B. | verification |
| C. | synthesis of large digital design |
| D. | all of the mentioned |
| Answer» E. | |
| 130. |
VHSIC stands for |
| A. | very high speed integrated circuits |
| B. | very higher speed integration circuits |
| C. | variable high speed integrated circuits |
| D. | variable higher speed integration circuits |
| Answer» B. very higher speed integration circuits | |
| 131. |
The full form of VHDL is |
| A. | very high descriptive language |
| B. | verilog hardware description language |
| C. | variable definition language |
| D. | none of the mentioned |
| Answer» C. variable definition language | |
| 132. |
The full form of HDL is |
| A. | higher descriptive language |
| B. | higher definition language |
| C. | hardware description language |
| D. | high descriptive language |
| Answer» D. high descriptive language | |
| 133. |
The enable input is also known as |
| A. | select input |
| B. | decoded input |
| C. | strobe |
| D. | sink |
| Answer» D. sink | |
| 134. |
In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is |
| A. | x0 |
| B. | x1 |
| C. | x2 |
| D. | x3 |
| Answer» C. x2 | |
| 135. |
How many NOT gates are required for the construction of a 4-to-1 multiplexer? |
| A. | 3 |
| B. | 4 |
| C. | 2 |
| D. | 5 |
| Answer» D. 5 | |
| 136. |
A basic multiplexer principle can be demonstrated through the use of a |
| A. | single-pole relay |
| B. | dpdt switch |
| C. | rotary switch |
| D. | linear stepper |
| Answer» D. linear stepper | |
| 137. |
If the number of n selected input lines is equal to 2^m then it requires            select lines. |
| A. | 2 |
| B. | m |
| C. | n |
| D. | 2n |
| Answer» C. n | |
| 138. |
In a multiplexer, the selection of a particular input line is controlled by |
| A. | data controller |
| B. | selected lines |
| C. | logic gates |
| D. | both data controller and selected lines |
| Answer» C. logic gates | |
| 139. |
How many select lines would be required for an 8- line-to-1-line multiplexer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 3 |
| Answer» E. | |
| 140. |
A digital multiplexer is a combinational circuit that selects |
| A. | one digital information from several sources and transmits the selected one |
| B. | many digital information and convert them into one |
| C. | many decimal inputs and transmits the selected information |
| D. | many decimal outputs and accepts the selected information |
| Answer» B. many digital information and convert them into one | |
| 141. |
One multiplexer can take the place of |
| A. | several ssi logic gates |
| B. | combinational logic circuits |
| C. | several ex-nor gates |
| D. | several ssi logic gates or combinational logic circuits |
| Answer» E. | |
| 142. |
What is the function of an enable input on a multiplexer chip? |
| A. | to apply vcc |
| B. | to connect ground |
| C. | to active the entire chip |
| D. | to active one half of the chip |
| Answer» D. to active one half of the chip | |
| 143. |
Which is the major functioning responsibility of the multiplexing combinational circuit? |
| A. | decoding the binary information |
| B. | generation of all minterms in an output function with or-gate |
| C. | generation of selected path between multiple sources and a single destination |
| D. | encoding of binary information |
| Answer» D. encoding of binary information | |
| 144. |
It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of |
| A. | inputs |
| B. | outputs |
| C. | selection lines |
| D. | enable lines |
| Answer» B. outputs | |
| 145. |
Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line? |
| A. | data selector |
| B. | data distributor |
| C. | both data selector and data distributor |
| D. | demultiplexer |
| Answer» B. data distributor | |
| 146. |
If two inputs are active on a priority encoder, which will be coded on the output? |
| A. | the higher value |
| B. | the lower value |
| C. | neither of the inputs |
| D. | both of the inputs |
| Answer» B. the lower value | |
| 147. |
What is a multiplexer? |
| A. | it is a type of decoder which decodes several inputs and gives one output |
| B. | a multiplexer is a device which converts many signals into one |
| C. | it takes one input and results into many output |
| D. | it is a type of encoder which decodes several inputs and gives one output |
| Answer» C. it takes one input and results into many output | |
| 148. |
The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as |
| A. | enable |
| B. | disable |
| C. | strobe |
| D. | clock |
| Answer» B. disable | |
| 149. |
Can an encoder be called as multiplexer? |
| A. | no |
| B. | yes |
| C. | sometimes |
| D. | never |
| Answer» C. sometimes | |
| 150. |
How many OR gates are required for an octal-to- binary encoder? |
| A. | 3 |
| B. | 2 |
| C. | 8 |
| D. | 10 |
| Answer» B. 2 | |