A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as

A user has designed JK flip flop by using the VHDL code. The output i

1.	A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as
A.	switching condition
B.	master slave condition
C.	race around condition
D.	edge triggered condition
Answer» D. edge triggered condition