MCQOPTIONS
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MCQOPTIONS
This section includes 358 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
A major advantage of DTL over the earlier resistor–transistor logic is the |
| A. | increased fan out |
| B. | increased fan in |
| C. | decreased fan out |
| D. | decreased fan in |
| Answer» C. decreased fan out | |
| 2. |
Moore machine has states than a mealy machine. |
| A. | fewer |
| B. | more |
| C. | equal |
| D. | negligible |
| Answer» C. equal | |
| 3. |
In D register, ‘D’ stands for |
| A. | delay |
| B. | decrement |
| C. | data |
| D. | decay |
| Answer» D. decay | |
| 4. |
State transition happens in every clock cycle. |
| A. | once |
| B. | twice |
| C. | thrice |
| D. | four times |
| Answer» B. twice | |
| 5. |
Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’? |
| A. | due to its capability to receive data from flip-flop |
| B. | due to its capability to store data in flip-flop |
| C. | due to its capability to transfer the data into flip-flop |
| D. | due to erasing the data from the flip-flop |
| Answer» D. due to erasing the data from the flip-flop | |
| 6. |
Each “0” entry in a K-map square represents: |
| A. | a high for each input truth table condition that produces a high output |
| B. | a high output on the truth table for all low input combinations |
| C. | a low output for all possible high input conditions |
| D. | a don’t care condition for all possible input truth table combinations |
| Answer» B. a high output on the truth table for all low input combinations | |
| 7. |
Binary subtraction of 101101 – 001011 = ? |
| A. | 100010 |
| B. | 010110 |
| C. | 110101 |
| D. | 101100 |
| Answer» B. 010110 | |
| 8. |
Each “1” entry in a K-map square represents: |
| A. | a high for each input truth table condition that produces a high output |
| B. | a high output on the truth table for all low input combinations |
| C. | a low output for all possible high input conditions |
| D. | a don’t care condition for all possible input truth table combinations |
| Answer» B. a high output on the truth table for all low input combinations | |
| 9. |
TTL circuits with “totem-pole” output stage minimize |
| A. | the power dissipation in rtl |
| B. | the time consumption in rtl |
| C. | the speed of transferring rate in rtl |
| D. | propagation delay in rtl |
| Answer» B. the time consumption in rtl | |
| 10. |
In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is |
| A. | no change |
| B. | set |
| C. | reset |
| D. | forbidden |
| Answer» B. set | |
| 11. |
100101 × 0110 = ? |
| A. | 1011001111 |
| B. | 0100110011 |
| C. | 101111110 |
| D. | 0110100101 |
| Answer» D. 0110100101 | |
| 12. |
Diode–transistor logic (DTL) is the direct ancestor of |
| A. | register-transistor logic |
| B. | transistor–transistor logic |
| C. | high threshold logic |
| D. | emitter coupled logic |
| Answer» C. high threshold logic | |
| 13. |
A NAND based S’-R’ latch can be converted into S-R latch by placing |
| A. | a d latch at each of its input |
| B. | an inverter at each of its input |
| C. | it can never be converted |
| D. | both a d latch and an inverter at its input |
| Answer» E. | |
| 14. |
Transistor–transistor logic (TTL) is a class of digital circuits built from |
| A. | jfet only |
| B. | bipolar junction transistors (bjt) |
| C. | resistors |
| D. | bipolar junction transistors (bjt) and resistors |
| Answer» E. | |
| 15. |
There are Minterms for 3 variables (a, b, c). |
| A. | 0 |
| B. | 2 |
| C. | 8 |
| D. | 1 |
| Answer» D. 1 | |
| 16. |
Which of the following can’t have multiple assignments or drivers? |
| A. | std_logic |
| B. | integer |
| C. | std_ulogic |
| D. | bit |
| Answer» D. bit | |
| 17. |
Binary subtraction of 100101 – 011110 is |
| A. | 000111 |
| B. | 111000 |
| C. | 010101 |
| D. | 101010 |
| Answer» B. 111000 | |
| 18. |
Mealy machines have states than Moore machine. |
| A. | fewer |
| B. | more |
| C. | equal |
| D. | negligible |
| Answer» B. more | |
| 19. |
The Boolean expression Y = (AB)’ is logically equivalent to what single gate? |
| A. | nand |
| B. | nor |
| C. | and |
| D. | or |
| Answer» B. nor | |
| 20. |
‘shift_reg’ is used to initialize the |
| A. | lsb |
| B. | msb |
| C. | register type |
| D. | register bits |
| Answer» C. register type | |
| 21. |
A ripple counter’s speed is limited by the propagation delay of |
| A. | each flip-flop |
| B. | all flip-flops and gates |
| C. | the flip-flops only with gates |
| D. | only circuit gates |
| Answer» B. all flip-flops and gates | |
| 22. |
The term synchronous means _ |
| A. | the output changes state only when any of the input is triggered |
| B. | the output changes state only when the clock input is triggered |
| C. | the output changes state only when the input is reversed |
| D. | the output changes state only when the input follows it |
| Answer» C. the output changes state only when the input is reversed | |
| 23. |
What is an ambiguous condition in a NAND based S’-R’ latch? |
| A. | s’=0, r’=1 |
| B. | s’=1, r’=0 |
| C. | s’=1, r’=1 |
| D. | s’=0, r’=0 |
| Answer» E. | |
| 24. |
Perform multiplication of the binary numbers: 01001 × 01011 = ? |
| A. | 001100011 |
| B. | 110011100 |
| C. | 010100110 |
| D. | 101010111 |
| Answer» B. 110011100 | |
| 25. |
Divide the binary numbers: 111101 ÷ 1001 and find the remainder |
| A. | 0010 |
| B. | 1010 |
| C. | 1100 |
| D. | 0011 |
| Answer» E. | |
| 26. |
Which of the following is not a combinational circuit? |
| A. | adder |
| B. | code convertor |
| C. | multiplexer |
| D. | counter |
| Answer» E. | |
| 27. |
Which of the following is a not a characteristics of combinational circuits? |
| A. | the output of combinational circuit depends on present input |
| B. | there is no use of clock signal in combinational circuits |
| C. | the output of combinational circuit depends on previous output |
| D. | there is no storage element in combinational circuit |
| Answer» D. there is no storage element in combinational circuit | |
| 28. |
Which of the following can’t have multiple assignments or drivers? |
| A. | std_logic |
| B. | integer |
| C. | std_ulogic |
| D. | bit |
| Answer» D. bit | |
| 29. |
Packages increases of the code. |
| A. | reusability |
| B. | readability |
| C. | managing |
| D. | resolution |
| Answer» B. readability | |
| 30. |
Which of the following is not a in-built package in VHDL? |
| A. | std_logic_1164 |
| B. | textio |
| C. | standard |
| D. | std |
| Answer» E. | |
| 31. |
Any item declared in a package declaration section are visible to |
| A. | every design unit |
| B. | package body only |
| C. | library containing that package |
| D. | design unit that use the package |
| Answer» E. | |
| 32. |
A package may consist of design units. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 33. |
Which of the following is true about packages? |
| A. | package is collection of libraries |
| B. | library is collection of packages |
| C. | package is collection of entities |
| D. | entity is collection of packages |
| Answer» C. package is collection of entities | |
| 34. |
In gated D latch, which of the following is the input symbol? |
| A. | d |
| B. | q |
| C. | en |
| D. | clk |
| Answer» B. q | |
| 35. |
Transfer of one bit of information at a time is called |
| A. | rotating |
| B. | serial transfer |
| C. | parallel transfer |
| D. | shifting |
| Answer» C. parallel transfer | |
| 36. |
Time taken by the shift register to transfer the content is called |
| A. | clock duration |
| B. | bit duration |
| C. | word duration |
| D. | duration |
| Answer» D. duration | |
| 37. |
Four bits shift register enables shift control signal in how many clock pulses? |
| A. | two clock pulses |
| B. | three clock pulses |
| C. | four clock pulses |
| D. | five clock pulses |
| Answer» D. five clock pulses | |
| 38. |
In PIPO shift register, parallel data can be taken out by |
| A. | using the q output of the first flip-flop |
| B. | using the q output of the last flip-flop |
| C. | using the q output of the second flip-flop |
| D. | using the q output of each flip-flop |
| Answer» E. | |
| 39. |
In serial input serial output register, the data of is accessed by the circuit. |
| A. | last flip-flop |
| B. | first flip-flop |
| C. | all flip-flops |
| D. | no flip-flop |
| Answer» C. all flip-flops | |
| 40. |
Shift registers comprise of which flip-flops? |
| A. | d flip-flops |
| B. | sr flip-flops |
| C. | jk flip-flops |
| D. | t flip-flops |
| Answer» B. sr flip-flops | |
| 41. |
Why we need to include all the input signals in the sensitivity list of the process? |
| A. | to monitor the output continuously |
| B. | to monitor the input continuously |
| C. | to make the circuit synthesizable by eda tools |
| D. | no special purpose |
| Answer» C. to make the circuit synthesizable by eda tools | |
| 42. |
The process statement used in combinational circuits is called process. |
| A. | combinational |
| B. | clocked |
| C. | unclocked |
| D. | sequential |
| Answer» B. clocked | |
| 43. |
In mealy type FSM, the path is labelled by which of the following? |
| A. | inputs |
| B. | outputs |
| C. | both inputs and outputs |
| D. | current state |
| Answer» D. current state | |
| 44. |
Mealy machines have states than Moore machine. |
| A. | fewer |
| B. | more |
| C. | equal |
| D. | negligible |
| Answer» B. more | |
| 45. |
What is the first state of FSM? |
| A. | wait loop state |
| B. | initial state |
| C. | output state |
| D. | activate pulse state |
| Answer» C. output state | |
| 46. |
What is the first step in writing the VHDL for an FSM? |
| A. | to define the vhdl entity |
| B. | naming the entity |
| C. | defining the data type |
| D. | creating the states |
| Answer» B. naming the entity | |
| 47. |
States in FSM are represented by |
| A. | bits |
| B. | bytes |
| C. | word |
| D. | character |
| Answer» B. bytes | |
| 48. |
What kind of output does mealy machine produce? |
| A. | asynchronous |
| B. | synchronous |
| C. | level |
| D. | pulsed |
| Answer» B. synchronous | |
| 49. |
Which of the following react faster to inputs? |
| A. | sequencer |
| B. | generators |
| C. | mealy machines |
| D. | moore machines |
| Answer» D. moore machines | |
| 50. |
State transition happens in every clock cycle. |
| A. | once |
| B. | twice |
| C. | thrice |
| D. | four times |
| Answer» B. twice | |