MCQOPTIONS
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MCQOPTIONS
This section includes 1271 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics & Communication Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
expressions can be implemented using either (1) 2-level AND- OR logic circuits or (2) 2-level NAND logic circuits. |
| A. | pos |
| B. | literals |
| C. | sop |
| D. | pos |
| Answer» D. pos | |
| 102. |
How many types of sequential circuits are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 103. |
1011)2 = (11.6875)10 |
| A. | (111101)2 |
| B. | (010100)2 |
| C. | (111100)2 |
| D. | (101010)2 |
| Answer» C. (111100)2 | |
| 104. |
The difference between a PAL & a PLA is |
| A. | pals and plas are the same thing |
| B. | the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane |
| C. | the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane |
| D. | the pal has more possible product terms than the pla |
| Answer» C. the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane | |
| 105. |
On subtracting +28 from +29 using 2’s complement, we get |
| A. | 11111010 |
| B. | 111111001 |
| C. | 100001 |
| D. | 1 |
| Answer» E. | |
| 106. |
The complex programmable logic device contains several PLD blocks and |
| A. | a language compiler |
| B. | and/or arrays |
| C. | global interconnection matrix |
| D. | field-programmable switches |
| Answer» D. field-programmable switches | |
| 107. |
Convert the binary number (01011.1011)2 into decimal: |
| A. | (11.6875)10 |
| B. | (11.5874)10 |
| C. | (10.9876)10 |
| D. | (10.7893)10 |
| Answer» B. (11.5874)10 | |
| 108. |
Full subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 8 bits |
| Answer» C. 4 bits | |
| 109. |
In four bit dynamic shift register output is obtained |
| A. | parallel output at inverters 1, 3, 5, 7 |
| B. | parallel output at inverters 1, 5, 8 |
| C. | parallel output at all inverters |
| D. | parallel output at inverter 2, 4, 6, 8 |
| Answer» E. | |
| 110. |
If A, B and C are the inputs of a full adder then the sum is given by |
| A. | a and b and c |
| B. | a or b and c |
| C. | a xor b xor c |
| D. | a or b or c |
| Answer» D. a or b or c | |
| 111. |
A decimal counter has states. |
| A. | 5 |
| B. | 10 |
| C. | 15 |
| D. | 20 |
| Answer» C. 15 | |
| 112. |
Which of the following circuit can be used as parallel to serial converter? |
| A. | multiplexer |
| B. | demultiplexer |
| C. | decoder |
| D. | digital counter |
| Answer» B. demultiplexer | |
| 113. |
is used to drive high capacitance load. |
| A. | single polar capability |
| B. | bipolar capability |
| C. | tripolar capability |
| D. | bi and tri polar capability |
| Answer» C. tripolar capability | |
| 114. |
There are cells in a 4-variable K- map. |
| A. | 12 |
| B. | 16 |
| C. | 18 |
| D. | 8 |
| Answer» C. 18 | |
| 115. |
Using the transformation method you can realize any POS realization of OR-AND with only. |
| A. | xor |
| B. | nand |
| C. | and |
| D. | nor |
| Answer» E. | |
| 116. |
The gate is an OR gate followed by a NOT gate. |
| A. | nand |
| B. | exor |
| C. | nor |
| D. | exnor |
| Answer» D. exnor | |
| 117. |
In S-R flip-flop, if Q = 0 the output is said to be |
| A. | set |
| B. | reset |
| C. | previous state |
| D. | current state |
| Answer» C. previous state | |
| 118. |
The selector inputs to an arithmetic/logic unit (ALU) determine the |
| A. | selection of the ic |
| B. | arithmetic or logic function |
| C. | data word selection |
| D. | clock frequency to be used |
| Answer» C. data word selection | |
| 119. |
On addition of +38 and -20 using 2’s complement, we get |
| A. | 11110001 |
| B. | 100001110 |
| C. | 010010 |
| D. | 110101011 |
| Answer» D. 110101011 | |
| 120. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» B. q’ output goes high | |
| 121. |
CD-ROM refers to |
| A. | floppy disk |
| B. | compact disk-read only memory |
| C. | compressed disk-read only memory |
| D. | compressed disk- random access memory |
| Answer» C. compressed disk-read only memory | |
| 122. |
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of |
| A. | 16 us |
| B. | 8 us |
| C. | 4 us |
| D. | 2 us |
| Answer» D. 2 us | |
| 123. |
As the temperature is increased, storage time |
| A. | halved |
| B. | doubled |
| C. | does not change |
| D. | tripled |
| Answer» B. doubled | |
| 124. |
How many AND, OR and EXOR gates are required for the configuration of full |
| A. | 1, 2, 2 |
| B. | 2, 1, 2 |
| C. | 3, 1, 2 |
| D. | 4, 0, 1 |
| Answer» C. 3, 1, 2 | |
| 125. |
Let A and B is the input of a subtractor then the borrow will be |
| A. | a and b’ |
| B. | a’ and b |
| C. | a or b |
| D. | a and b |
| Answer» C. a or b | |
| 126. |
A is a circuit with only one output but can have multiple inputs. |
| A. | logic gate |
| B. | truth table |
| C. | binary circuit |
| D. | boolean circuit |
| Answer» B. truth table | |
| 127. |
What is a fusing process? |
| A. | it is a process by which data is passed to the memory |
| B. | it is a process by which data is read through the memory |
| C. | it is a process by which programs are burnout to the diode/transistors |
| D. | it is a process by which data is fetched through the memory |
| Answer» D. it is a process by which data is fetched through the memory | |
| 128. |
The equivalent of emitter-coupled logic made out of FETs is called |
| A. | cml |
| B. | scfl |
| C. | fecl |
| D. | efcl |
| Answer» C. fecl | |
| 129. |
If A, B and C are the inputs of a full adder then the carry is given by |
| A. | a and b or (a or b) and c |
| B. | a or b or (a and b) c |
| C. | (a and b) or (a and b)c |
| D. | a xor b xor (a xor b) and c |
| Answer» B. a or b or (a and b) c | |
| 130. |
3 CYCLES AND RACES, STATE REDUCTION |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 131. |
29 input circuit will have total of |
| A. | 32 entries |
| B. | 128 entries |
| C. | 256 entries |
| D. | 512 entries |
| Answer» E. | |
| 132. |
Another way to connect devices to a shared data bus is to use a |
| A. | circulating gate |
| B. | transceiver |
| C. | bidirectional encoder |
| D. | strobed latch |
| Answer» C. bidirectional encoder | |
| 133. |
Output values of Moore type FSM are determined by its |
| A. | input values |
| B. | output values |
| C. | clock input |
| D. | current state |
| Answer» E. | |
| 134. |
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops? |
| A. | 0 to 2n |
| B. | 0 to 2n + 1 |
| C. | 0 to 2n – 1 d) 0 to 2n+1/2 |
| Answer» D. | |
| 135. |
The only function of NOT gate is to ___________. |
| A. | Stop signal |
| B. | Invert input signal |
| C. | Act as a universal gate |
| D. | None of the above |
| Answer» C. Act as a universal gate | |
| 136. |
The number 10000 would appear just immediately after |
| A. | FFFF (hex) |
| B. | 1111 (binary) |
| C. | 7777 (octal) |
| D. | All of the above |
| Answer» E. | |
| 137. |
Consider the representation of six-bit numbers by two’s complement, one’s complement, or by sign and magnitude: In which representation is there overflow from the addition of the integers 011000 and 011000? |
| A. | Two’s complement only |
| B. | Sign and magnitude and one’s complement only |
| C. | Two’s complement and one’s complement only |
| D. | All three representations |
| Answer» E. | |
| 138. |
When an input signal 1 is applied to a NOT gate, the output is ___________. |
| A. | 0 |
| B. | 1 |
| C. | Either 0 & 1 |
| D. | None of the above |
| Answer» B. 1 | |
| 139. |
A hexadecimal odometer displays F 52 F. The next reading will be |
| A. | F52E |
| B. | G52F |
| C. | F53F |
| D. | F53O |
| Answer» E. | |
| 140. |
In Boolean algebra, the bar sign (-) indicates ___________. |
| A. | OR operation |
| B. | AND operation |
| C. | NOT operation |
| D. | None of the above |
| Answer» D. None of the above | |
| 141. |
The NAND gate is AND gate followed by ___________. |
| A. | NOT gate |
| B. | OR gate |
| C. | AND gate |
| D. | None of the above |
| Answer» B. OR gate | |
| 142. |
The inputs of a NAND gate are connected together. The resulting circuit is ___________. |
| A. | OR gate |
| B. | AND gate |
| C. | NOT gate |
| D. | None of the above |
| Answer» D. None of the above | |
| 143. |
Which is the correct order of sequence for representing the input values in K-map? |
| A. | (00, 01, 10, 11) |
| B. | (00, 10, 01, 11) |
| C. | (00, 01, 11, 10) |
| D. | (00, 10, 11, 01) |
| Answer» D. (00, 10, 11, 01) | |
| 144. |
What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view? |
| A. | Input operation |
| B. | Tristate output operation |
| C. | Bi-directional I/O pin access |
| D. | All of the above |
| Answer» E. | |
| 145. |
The inverter is ___________ |
| A. | NOT gate |
| B. | OR gate |
| C. | AND gate |
| D. | None of the above |
| Answer» B. OR gate | |
| 146. |
A debouncing circuit is |
| A. | An astable MV |
| B. | A bistable MV |
| C. | A latch |
| D. | A monostable MV |
| Answer» D. A monostable MV | |
| 147. |
"What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA?A. Propagation delay will increaseB. FPGA area will increaseC. Wastage of logic modules will not be preventedD. Number of interconnected paths in device will decrease" |
| A. | A & B |
| B. | C & D |
| C. | A & D |
| D. | B & C |
| Answer» B. C & D | |
| 148. |
The NOR gate is OR gate followed by ___________. |
| A. | AND gate |
| B. | NAND gate |
| C. | NOT gate |
| D. | None of the above |
| Answer» D. None of the above | |
| 149. |
Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins? |
| A. | PLCC |
| B. | QFP |
| C. | PGA |
| D. | BGA |
| Answer» E. | |
| 150. |
Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is. |
| A. | 10 CPS |
| B. | 120 CPS |
| C. | 12 CPS |
| D. | None of the above |
| Answer» D. None of the above | |