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MCQOPTIONS
This section includes 1271 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics & Communication Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS. |
| A. | six, eight |
| B. | eight, six |
| C. | five, six |
| D. | six, five |
| Answer» B. eight, six | |
| 52. |
What happens if the input is high in FSM? |
| A. | change of state |
| B. | no transition in state |
| C. | remains in a single state |
| D. | invalid state |
| Answer» B. no transition in state | |
| 53. |
The expression of a NAND gate is |
| A. | a.b |
| B. | a’b+ab’ |
| C. | (a.b)’ |
| D. | (a+b)’ |
| Answer» D. (a+b)’ | |
| 54. |
The octal number (651.124)8 is equivalent to |
| A. | 16 |
| B. | (1b0.10)16 |
| C. | (1a8.a3)16 |
| D. | (1b0.b0)16 |
| Answer» B. (1b0.10)16 | |
| 55. |
If the number of n selected input lines is equal to 2^m then it requires select lines. |
| A. | 2 |
| B. | m |
| C. | n |
| D. | 2n |
| Answer» C. n | |
| 56. |
To read from the memory, the select input and the power down/program input must be |
| A. | high |
| B. | low |
| C. | sometimes high and sometimes low |
| D. | alternate high and low |
| Answer» C. sometimes high and sometimes low | |
| 57. |
4 to 1 MUX would have |
| A. | 2 inputs |
| B. | 3 inputs |
| C. | 4 inputs |
| D. | 5 inputs |
| Answer» D. 5 inputs | |
| 58. |
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing |
| A. | 1101 |
| B. | 0111 |
| C. | 0001 |
| D. | 1110 |
| Answer» C. 0001 | |
| 59. |
Complement of F’ gives back |
| A. | f’ |
| B. | f |
| C. | ff |
| D. | ff’ |
| Answer» C. ff | |
| 60. |
A large memory is compressed into a small one by using |
| A. | lsi semiconductor |
| B. | vlsi semiconductor |
| C. | cdr semiconductor |
| D. | ssi semiconductor |
| Answer» C. cdr semiconductor | |
| 61. |
The binary subtraction of 0 – 0 = ? |
| A. | difference = 0, borrow = 0 |
| B. | difference = 1, borrow = 0 |
| C. | difference = 1, borrow = 1 |
| D. | difference = 0, borrow = 1 |
| Answer» B. difference = 1, borrow = 0 | |
| 62. |
The inputs/outputs of an analog multiplexer/demultiplexer are |
| A. | bidirectional |
| B. | unidirectional |
| C. | even parity |
| D. | binary-coded decimal |
| Answer» B. unidirectional | |
| 63. |
An identify comparator is defined as a digital comparator which has |
| A. | only one output terminal |
| B. | two output terminals |
| C. | three output terminals |
| D. | no output terminal |
| Answer» B. two output terminals | |
| 64. |
The Output is LOW if any one of the inputs is HIGH in case of a gate. |
| A. | nor |
| B. | nand |
| C. | or |
| D. | and |
| Answer» C. or | |
| 65. |
A basic multiplexer principle can be demonstrated through the use of a |
| A. | single-pole relay |
| B. | dpdt switch |
| C. | rotary switch |
| D. | linear stepper |
| Answer» D. linear stepper | |
| 66. |
Simplify Y = AB’ + (A’ + B)C. |
| A. | ab’ + c |
| B. | ab + ac |
| C. | a’b + ac’ |
| D. | ab + a |
| Answer» B. ab + ac | |
| 67. |
A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains |
| A. | 0000 |
| B. | 1111 |
| C. | 0111 |
| D. | 1000 |
| Answer» D. 1000 | |
| 68. |
How many select lines are required for a 1- to-8 demultiplexer? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 69. |
If a PAL has been programmed once |
| A. | its logic capacity is lost |
| B. | its outputs are only active high |
| C. | its outputs are only active low |
| D. | it cannot be reprogrammed |
| Answer» E. | |
| 70. |
The full form of SCFL is |
| A. | source-collector logic |
| B. | source-coupled logic |
| C. | source-complementary logic |
| D. | source cored logic |
| Answer» C. source-complementary logic | |
| 71. |
In case of XOR/XNOR simplification we have to look for the following |
| A. | diagonal adjacencies |
| B. | offset adjacencies |
| C. | straight adjacencies |
| D. | both diagonal and offset adjencies |
| Answer» E. | |
| 72. |
There are Minterms for 3 variables (a, b, c). |
| A. | 0 |
| B. | 2 |
| C. | 8 |
| D. | 1 |
| Answer» D. 1 | |
| 73. |
Ring shift and Johnson counters are |
| A. | synchronous counters |
| B. | asynchronous counters |
| C. | true binary counters |
| D. | synchronous and true binary counters |
| Answer» B. asynchronous counters | |
| 74. |
Logic circuits can also be designed using |
| A. | ram |
| B. | rom |
| C. | pld |
| D. | pla |
| Answer» D. pla | |
| 75. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» D. j and k | |
| 76. |
What is data routing in a multiplexer? |
| A. | it spreads the information to the control unit |
| B. | it can be used to route data from one of several source to destination |
| C. | it is an application of multiplexer |
| D. | both it can be used to route data and it is an application of multiplexer |
| Answer» E. | |
| 77. |
In the FSM diagram, what does the information below the line in the circle represent? |
| A. | change of state |
| B. | state |
| C. | output value |
| D. | initial state |
| Answer» D. initial state | |
| 78. |
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in |
| A. | 4 μs |
| B. | 40 μs |
| C. | 400 μs |
| D. | 40 ms |
| Answer» C. 400 μs | |
| 79. |
The decimal equivalent of the excess-3 number 110010100011.01110101 is |
| A. | 970.42 |
| B. | 1253.75 |
| C. | 861.75 |
| D. | 1132.87 |
| Answer» B. 1253.75 | |
| 80. |
Static RAM employs |
| A. | bjt or mosfet |
| B. | fet or jfet |
| C. | capacitor or bjt |
| D. | bjt or mos |
| Answer» E. | |
| 81. |
The NAND latch works when both inputs are |
| A. | 1 |
| B. | 0 |
| C. | inverted |
| D. | don’t cares |
| Answer» B. 0 | |
| 82. |
How many types of RAMs are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 83. |
In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be |
| A. | y0 |
| B. | y1 |
| C. | y2 |
| D. | y3 |
| Answer» E. | |
| 84. |
One example of the use of an S-R flip-flop is as |
| A. | transition pulse generator |
| B. | racer |
| C. | switch debouncer |
| D. | astable oscillator |
| Answer» D. astable oscillator | |
| 85. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» E. | |
| 86. |
The parallel outputs of a counter circuit represent the |
| A. | parallel data word |
| B. | clock frequency |
| C. | counter modulus |
| D. | clock count |
| Answer» E. | |
| 87. |
VLSI chip utilizes |
| A. | nmos |
| B. | cmos |
| C. | bjt |
| D. | all of the mentioned |
| Answer» E. | |
| 88. |
The primary purpose of a three-state buffer is usually |
| A. | to provide isolation between the input device and the data bus |
| B. | to provide the sink or source current required by any device connected to its output without loading down the output device |
| C. | temporary data storage |
| D. | to control data flow |
| Answer» B. to provide the sink or source current required by any device connected to its output without loading down the output device | |
| 89. |
State transition happens in every clock cycle. |
| A. | once |
| B. | twice |
| C. | thrice |
| D. | four times |
| Answer» B. twice | |
| 90. |
Maxterm is the sum of of the corresponding Minterm with its literal complemented. |
| A. | terms |
| B. | words |
| C. | numbers |
| D. | nibble |
| Answer» B. words | |
| 91. |
The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains |
| A. | 01110 |
| B. | 00001 |
| C. | 00101 |
| D. | 00110 |
| Answer» D. 00110 | |
| 92. |
The output of a full subtractor is same as |
| A. | half adder |
| B. | full adder |
| C. | half subtractor |
| D. | decoder |
| Answer» C. half subtractor | |
| 93. |
How many types of digital comparators are? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 94. |
6 MULTIPLEXER |
| A. | to apply vcc |
| B. | to connect ground |
| C. | to active the entire chip |
| D. | to active one half of the chip |
| Answer» D. to active one half of the chip | |
| 95. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» C. label states | |
| 96. |
Data stored in an electronic memory cell can be accessed at random and on demand |
| A. | erom |
| B. | ram |
| C. | prom |
| D. | eeprom |
| Answer» B. ram | |
| 97. |
DeMorgan’s theorem states that |
| A. | (ab)’ = a’ + b’ |
| B. | (a + b)’ = a’ * b |
| C. | a’ + b’ = a’b’ |
| D. | (ab)’ = a’ + b |
| Answer» B. (a + b)’ = a’ * b | |
| 98. |
Moore machine has states than a mealy machine. |
| A. | fewer |
| B. | more |
| C. | equal |
| D. | negligible |
| Answer» C. equal | |
| 99. |
The basic latch consists of |
| A. | two inverters |
| B. | two comparators |
| C. | two amplifiers |
| D. | two adders |
| Answer» B. two comparators | |
| 100. |
Which one of the following is used for the fabrication of MOS EPROM? |
| A. | tms 2513 |
| B. | tms 2515 |
| C. | tms 2516 |
| D. | tms 2518 |
| Answer» D. tms 2518 | |