MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 501. |
In SDRAM’s buffers are used to store data that is read or written. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 502. |
To improve the data retrieval rate |
| A. | access time |
| B. | cycle time |
| C. | memory latency |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 503. |
DDR SDRAM’s perform faster data transfer by |
| A. | integrating the hardware |
| B. | transferring on both edges |
| C. | improving the clock speeds |
| D. | increasing the bandwidth |
| Answer» C. improving the clock speeds | |
| 504. |
In a SDRAM each row is refreshed every 64ms. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 505. |
A Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â is used to restore the contents of the cells. |
| A. | sense amplifier |
| B. | refresh counter |
| C. | restorer |
| D. | none of the mentioned |
| Answer» C. restorer | |
| 506. |
The mode register is used to |
| A. | select the row or column data transfer mode |
| B. | select the mode of operation |
| C. | select mode of storing the data |
| D. | all of the mentioned |
| Answer» C. select mode of storing the data | |
| 507. |
The difference between DRAM’s and SDRAM’s is/are |
| A. | the dram’s will not use the master slave relationship in data transfer |
| B. | the sdram’s make use of clock |
| C. | the sdram’s are more power efficient |
| D. | none of the mentioned |
| Answer» E. | |
| 508. |
The block transfer capability of the DRAM is called |
| A. | burst mode |
| B. | block mode |
| C. | fast page mode |
| D. | fast frame mode |
| Answer» D. fast frame mode | |
| 509. |
The difference in the address and data connection between DRAM’s and SDRAM’s is |
| A. | the usage of more number of pins in sdram’s |
| B. | the requirement of more address lines in sdram’s |
| C. | the usage of a buffer in sdram’s |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 510. |
In order to read multiple bytes of a row at the same time, we make use of |
| A. | latch |
| B. | shift register |
| C. | cache |
| D. | memory extension |
| Answer» B. shift register | |
| 511. |
To get the row address of the required data               is enabled. |
| A. | cas |
| B. | ras |
| C. | cs |
| D. | sense/write |
| Answer» C. cs | |
| 512. |
The processor must take into account the delay in accessing the memory location, such memories are called |
| A. | delay integrated |
| B. | asynchronous memories |
| C. | synchronous memories |
| D. | isochronous memories |
| Answer» C. synchronous memories | |
| 513. |
                    circuit is used to restore the capacitor value. |
| A. | sense amplify |
| B. | signal amplifier |
| C. | delta modulator |
| D. | none of the mentioned |
| Answer» B. signal amplifier | |
| 514. |
The capacitors lose the charge over time due to |
| A. | the leakage resistance of the capacitor |
| B. | the small current in the transistor after being turned on |
| C. | the defect of the capacitor |
| D. | none of the mentioned |
| Answer» B. the small current in the transistor after being turned on | |
| 515. |
To reduce the number of external connections required, we make use of |
| A. | de-multiplexer |
| B. | multiplexer |
| C. | encoder |
| D. | decoder |
| Answer» C. encoder | |
| 516. |
The Reason for the disregarding of the SRAM’s is |
| A. | low efficiency |
| B. | high power consumption |
| C. | high cost |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 517. |
In a 4M-bit chip organisation has a total of 19 external connections.then it has                 address if 8 data lines are there. |
| A. | 10 |
| B. | 8 |
| C. | 9 |
| D. | 12 |
| Answer» D. 12 | |
| 518. |
The reason for the cells to lose their state over time is |
| A. | the lower voltage levels |
| B. | usage of capacitors to store the charge |
| C. | use of shift registers |
| D. | none of the mentioned |
| Answer» C. use of shift registers | |
| 519. |
The disadvantage of DRAM over SRAM is/are |
| A. | lower data storage capacities |
| B. | higher heat dissipation |
| C. | the cells are not static |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 520. |
The advantage of CMOS SRAM over the transistor one’s is |
| A. | low cost |
| B. | high efficiency |
| C. | high durability |
| D. | low power consumption |
| Answer» E. | |
| 521. |
Circuits that can hold their state as long as power is applied is |
| A. | dynamic memory |
| B. | static memory |
| C. | register |
| D. | cache |
| Answer» C. register | |
| 522. |
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into |
| A. | 128 x 8 |
| B. | 256 x 4 |
| C. | 512 x 2 |
| D. | 1024 x 1 |
| Answer» E. | |
| 523. |
The number of external connections required in 16 X 8 memory organisation is |
| A. | 14 |
| B. | 19 |
| C. | 15 |
| D. | 12 |
| Answer» B. 19 | |
| 524. |
A 16 X 8 Organisation of memory cells, can store upto |
| A. | 256 bits |
| B. | 1024 bits |
| C. | 512 bits |
| D. | 128 bits |
| Answer» E. | |
| 525. |
The word line is driven by the |
| A. | chip select |
| B. | address decoder |
| C. | data line |
| D. | control line |
| Answer» C. data line | |
| 526. |
The cells in a row are connected to a common line called |
| A. | work line |
| B. | word line |
| C. | length line |
| D. | principle diagonal |
| Answer» C. length line | |
| 527. |
VLSI stands for |
| A. | very large scale integration |
| B. | very large stand-alone integration |
| C. | volatile layer system interface |
| D. | none of the mentioned |
| Answer» B. very large stand-alone integration | |
| 528. |
The logical addresses generated by the cpu are mapped onto physical memory by |
| A. | relocation register |
| B. | tlb |
| C. | mmu |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 529. |
The cells in each column are connected to |
| A. | word line |
| B. | data line |
| C. | read line |
| D. | sense/ write line |
| Answer» E. | |
| 530. |
The minimum time delay between two successive memory read operations is |
| A. | cycle time |
| B. | latency |
| C. | delay |
| D. | none of the mentioned |
| Answer» B. latency | |
| 531. |
                      is the bottleneck, when it comes computer performance. |
| A. | memory access time |
| B. | memory cycle time |
| C. | delay |
| D. | latency |
| Answer» C. delay | |
| 532. |
The duration between the read and the mfc signal is |
| A. | access time |
| B. | latency |
| C. | delay |
| D. | cycle time |
| Answer» B. latency | |
| 533. |
EPIC stands for? |
| A. | explicitly parallel instruction computing |
| B. | external peripheral integrating component |
| C. | external parallel instruction computing |
| D. | none of the mentioned |
| Answer» B. external peripheral integrating component | |
| 534. |
In VLIW the decision for the order of execution of the instructions depends on the program itself. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 535. |
To compute the direction of the branch the VLIW uses |
| A. | seekers |
| B. | heuristics |
| C. | direction counter |
| D. | compass |
| Answer» C. direction counter | |
| 536. |
The main difference between the VLIW and the other approaches to improve performance is |
| A. | cost effectiveness |
| B. | increase in performance |
| C. | lack of complex hardware design |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 537. |
The VLIW processors are much simpler as they do not require of |
| A. | computational register |
| B. | complex logic circuits |
| C. | ssd slots |
| D. | scheduling hardware |
| Answer» E. | |
| 538. |
VLIW stands for? |
| A. | very long instruction word |
| B. | very long instruction width |
| C. | very large instruction word |
| D. | very long instruction width |
| Answer» B. very long instruction width | |
| 539. |
The parallel execution of operations in VLIW is done according to the schedule determined by |
| A. | task scheduler |
| B. | interpreter |
| C. | compiler |
| D. | encoder |
| Answer» D. encoder | |
| 540. |
The most common modes of communication in clusters are |
| A. | message queues |
| B. | message passing interface |
| C. | pvm |
| D. | both message passing interface and pvm |
| Answer» E. | |
| 541. |
In the client server model of the cluster                     approach is used. |
| A. | load configuration |
| B. | fifo |
| C. | bankers algorithm |
| D. | round robin |
| Answer» E. | |
| 542. |
The method followed in case of node failure, wherein the node gets disabled is |
| A. | stonith |
| B. | fibre channel |
| C. | fencing |
| D. | none of the mentioned |
| Answer» B. fibre channel | |
| 543. |
The cluster formation in which the work is divided equally among the systems is |
| A. | load-configuration |
| B. | load-division |
| C. | light head |
| D. | both load-configuration and load- division |
| Answer» B. load-division | |
| 544. |
The software which governs the group of computers is |
| A. | driver rd45 |
| B. | interface ui |
| C. | clustering middleware |
| D. | distributor |
| Answer» D. distributor | |
| 545. |
The computer cluster architecture emerged as a result of |
| A. | isa |
| B. | workstation |
| C. | super computers |
| D. | distributed systems |
| Answer» E. | |
| 546. |
Each computer in a cluster is connected using |
| A. | utp |
| B. | rj-45 |
| C. | stp |
| D. | coaxial cable |
| Answer» C. stp | |
| 547. |
The set of loosely connected computers are called as |
| A. | lan |
| B. | wan |
| C. | workstation |
| D. | cluster |
| Answer» E. | |
| 548. |
The algorithm followed in most of the systems to perform out of order execution is |
| A. | tomasulo algorithm |
| B. | score carding |
| C. | reader-writer algorithm |
| D. | none of the mentioned |
| Answer» B. score carding | |
| 549. |
The problem where process concurrency becomes an issue is called as |
| A. | philosophers problem |
| B. | bakery problem |
| C. | bankers problem |
| D. | reader-writer problem |
| Answer» E. | |
| 550. |
                          method is used in centralized systems to perform out of order execution. |
| A. | scorecard |
| B. | score boarding |
| C. | optimizing |
| D. | redundancy |
| Answer» C. optimizing | |