MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 551. |
The pipeline bubbling is a method used to prevent data hazard and structural hazards. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 552. |
The stalling of the processor due to the unavailability of the instructions is called as |
| A. | control hazard |
| B. | structural hazard |
| C. | input hazard |
| D. | none of the mentioned |
| Answer» B. structural hazard | |
| 553. |
Any condition that causes a processor to stall is called as |
| A. | hazard |
| B. | page fault |
| C. | system error |
| D. | none of the mentioned |
| Answer» B. page fault | |
| 554. |
The division operation in IA-32 is a single operand instruction so it is assumed that |
| A. | the divisor is stored in the eax register |
| B. | the dividend is stored in the eac register |
| C. | the divisor is stored in the accumulator |
| D. | the dividend is stored in the accumulator |
| Answer» B. the dividend is stored in the eac register | |
| 555. |
The MMX (Multimedia Extension) operands are stored in |
| A. | general purpose registers |
| B. | banked registers |
| C. | float point registers |
| D. | graphic registers |
| Answer» D. graphic registers | |
| 556. |
In case of multimedia extension instructions, the pixels are encoded into a data item of |
| A. | 16 bit |
| B. | 32 bit |
| C. | 24 bit |
| D. | 8 bit |
| Answer» E. | |
| 557. |
The instruction used to multiply operands yielding a double integer outcome is |
| A. | mul |
| B. | imul |
| C. | dmul |
| D. | emul |
| Answer» C. dmul | |
| 558. |
.data directive is used |
| A. | to indicate the ending of the data section |
| B. | to indicate the beginning of the data section |
| C. | to declare all the source operands |
| D. | to initialize the operands |
| Answer» C. to declare all the source operands | |
| 559. |
                      instruction is used to check the bit of the condition flags. |
| A. | test |
| B. | tb |
| C. | check |
| D. | bt |
| Answer» E. | |
| 560. |
SIMD stands for |
| A. | single instruction multiple data |
| B. | simple instruction multiple decoding |
| C. | sequential instruction multiple decoding |
| D. | system information mutable data |
| Answer» B. simple instruction multiple decoding | |
| 561. |
The instruction used to cause unconditional jump is |
| A. | ujg |
| B. | jg |
| C. | jmp |
| D. | goto |
| Answer» D. goto | |
| 562. |
The bit present in the op code, indicating which of the operands is the source is called as |
| A. | src bit |
| B. | indirection bit |
| C. | direction bit |
| D. | frm bit |
| Answer» D. frm bit | |
| 563. |
The instructions of IA-32 machines are of length up to |
| A. | 4 bytes |
| B. | 8 bytes |
| C. | 16 bytes |
| D. | 12 bytes |
| Answer» E. | |
| 564. |
The LEA mnemonic is used to |
| A. | load the effective address of an instruction |
| B. | load the values of operands onto an accumulator |
| C. | declare the values as global constants |
| D. | store the outcome of the operation at a memory location |
| Answer» B. load the values of operands onto an accumulator | |
| 565. |
The instruction JG loop does |
| A. | jumps to the memory location loop if the result of the most recent arithmetic op is even |
| B. | jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 |
| C. | jumps to the memory location loop if the test condition is satisfied with the value of loop |
| D. | none of the mentioned |
| Answer» C. jumps to the memory location loop if the test condition is satisfied with the value of loop | |
| 566. |
The instruction, ADD R1, R2, R3 is decoded as |
| A. | r1<-[r1]+[r2]+[r3] |
| B. | r3<-[r1]+[r2] |
| C. | r3<-[r1]+[r2]+[r3] |
| D. | r1<-[r2]+[r3] |
| Answer» E. | |
| 567. |
The Bit extension of the register is denoted with the help of                       symbol. |
| A. | $ |
| B. | ` |
| C. | e |
| D. | ~ |
| Answer» D. ~ | |
| 568. |
The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 569. |
The register used to serve as PC is called as |
| A. | indirection register |
| B. | instruction pointer |
| C. | r-32 |
| D. | none of the mentioned |
| Answer» C. r-32 | |
| 570. |
In IA-32 architecture along with the general flags, the other conditional flags provided are |
| A. | iopl |
| B. | if |
| C. | tf |
| D. | all of the mentioned |
| Answer» E. | |
| 571. |
IOPL stands for |
| A. | input/output privilege level |
| B. | input output process link |
| C. | internal output process link |
| D. | internal offset privilege level |
| Answer» B. input output process link | |
| 572. |
The PC is incorporated with the help of general purpose registers. |
| A. | true |
| B. | false |
| Answer» C. | |
| 573. |
The floating point numbers are stored in general purpose register in IA-32. |
| A. | true |
| B. | false |
| Answer» C. | |
| 574. |
The size of the floating registers can be extended upto |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» D. 64 bit | |
| 575. |
The pseudo instruction used to load an address into the register is |
| A. | load |
| B. | adr |
| C. | assign |
| D. | psload |
| Answer» C. assign | |
| 576. |
                        directive is used to name the register used for execution of an instruction. |
| A. | assign |
| B. | rn |
| C. | name |
| D. | declare |
| Answer» C. name | |
| 577. |
                        directives are used to initialize operands. |
| A. | int |
| B. | dataword |
| C. | reserve |
| D. | dcd |
| Answer» E. | |
| 578. |
                        directive specifies the start of the execution. |
| A. | start |
| B. | entry |
| C. | main |
| D. | origin |
| Answer» C. main | |
| 579. |
                      directive is used to indicate the beginning of the program instruction or data. |
| A. | equ |
| B. | start |
| C. | area |
| D. | space |
| Answer» D. space | |
| 580. |
The condition to check whether the branch should happen or not is given by |
| A. | the lower order 8 bits of the instruction |
| B. | the higher order 4 bits of the instruction |
| C. | the lower order 4 bits of the instruction |
| D. | the higher order 8 bits of the instruction |
| Answer» C. the lower order 4 bits of the instruction | |
| 581. |
The offset used in the conditional branching is                       bit. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 8 |
| Answer» B. 32 | |
| 582. |
The instruction, MLA R0,R1,R2,R3 performs |
| A. | r0<-[r1]+[r2]+[r3] |
| B. | r3<-[r0]+[r1]+[r2] |
| C. | r0<-[r1]*[r2]+[r3] |
| D. | r3<-[r0]*[r1]+[r2] |
| Answer» D. r3<-[r0]*[r1]+[r2] | |
| 583. |
                    instruction is used to get the 1’s complement of the operand. |
| A. | comp |
| B. | bic |
| C. | ~cmp |
| D. | mvn |
| Answer» E. | |
| 584. |
                        symbol is used to signify write back mode. |
| A. | # |
| B. | ^ |
| C. | & |
| D. | ! |
| Answer» E. | |
| 585. |
The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is |
| A. | ea = [rn] |
| B. | ea = [rn + rm] |
| C. | ea = [rn] + rm |
| D. | ea = [rm] + rn |
| Answer» B. ea = [rn + rm] | |
| 586. |
The addressing mode where the EA of the operand is the contents of Rn is |
| A. | pre-indexed mode |
| B. | pre-indexed with write back mode |
| C. | post-indexed mode |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 587. |
All instructions in ARM are conditionally executed. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 588. |
The banked registers are used for |
| A. | switching between supervisor and interrupt mode |
| B. | extended storing |
| C. | same as other general purpose registers |
| D. | none of the mentioned |
| Answer» B. extended storing | |
| 589. |
Each instruction in ARM machines is encoded into                       Word. |
| A. | 2 byte |
| B. | 3 byte |
| C. | 4 byte |
| D. | 8 byte |
| Answer» D. 8 byte | |
| 590. |
The additional duplicate register used in ARM machines are called as |
| A. | copied-registers |
| B. | banked registers |
| C. | extra registers |
| D. | extential registers |
| Answer» C. extra registers | |
| 591. |
RISC stands for |
| A. | restricted instruction sequencing computer |
| B. | restricted instruction sequential compiler |
| C. | reduced instruction set computer |
| D. | reduced induction set computer |
| Answer» D. reduced induction set computer | |
| 592. |
The address system supported by ARM systems is/are |
| A. | little endian |
| B. | big endian |
| C. | x-little endian |
| D. | both little & big endian |
| Answer» E. | |
| 593. |
The address space in ARM is |
| A. | 224 |
| B. | 264 |
| C. | 216 |
| D. | 232 |
| Answer» E. | |
| 594. |
In the ARM, PC is implemented using |
| A. | caches |
| B. | heaps |
| C. | general purpose register |
| D. | stack |
| Answer» D. stack | |
| 595. |
ARM stands for |
| A. | advanced rate machines |
| B. | advanced risc machines |
| C. | artificial running machines |
| D. | aviary running machines |
| Answer» C. artificial running machines | |
| 596. |
The ARM processors don’t support Byte addressability. |
| A. | true |
| B. | false |
| Answer» C. | |
| 597. |
ARM processors where basically designed for |
| A. | main frame systems |
| B. | distributed systems |
| C. | mobile systems |
| D. | super computers |
| Answer» D. super computers | |
| 598. |
The main importance of ARM micro- processors is providing operation with |
| A. | low cost and low power consumption |
| B. | higher degree of multi-tasking |
| C. | lower error or glitches |
| D. | efficient memory management |
| Answer» B. higher degree of multi-tasking | |
| 599. |
The LINK instruction is always followed by                           instruction. |
| A. | mov |
| B. | unlk |
| C. | org |
| D. | movem |
| Answer» E. | |
| 600. |
                          instruction is used to set up a frame pointer for the subroutines in 68000. |
| A. | create |
| B. | link |
| C. | unlk |
| D. | frame |
| Answer» C. unlk | |