950 + Mcqs in Computer Architecture Page 9 McqOptions

401.	The disadvantage/s of the hardwired approach is
A.	it is less flexible
B.	it cannot be used for complex instructions
C.	it is costly
D.	less flexible & cannot be used for complex instructions
Answer» E.

Discussion

402.	The benefit of using this approach is
A.	it is cost effective
B.	it is highly efficient
C.	it is very reliable
D.	it increases the speed of operation
Answer» E.

Discussion

403.	BRâ€¦
A.	true
B.	false
Answer» B. false

Discussion

404.	What does the end instruction do?
A.	it ends the generation of a signal
B.	it ends the complete generation process
C.	it starts a new instruction fetch cycle and resets the counter
D.	it is used to shift the control to the processor
Answer» D. it is used to shift the control to the processor

Discussion

405.	The name hardwired came because the sequence of operations carried out is determined by the wiring.
A.	true
B.	false
Answer» B. false

Discussion

406.	Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â are the different type/s of generating control signals.
A.	micro-programmed
B.	hardwired
C.	micro-instruction
D.	both micro-programmed and hardwired
Answer» E.

Discussion

407.	What does the hardwired control generator consist of?
A.	decoder/encoder
B.	condition codes
C.	control step counter
D.	all of the mentioned
Answer» E.

Discussion

408.	The type of control signal is generated based on
A.	contents of the step counter
B.	contents of ir
C.	contents of condition flags
D.	all of the mentioned
Answer» E.

Discussion

409.	There exists a separate block to increment the PC in multiple BUS organisation.
A.	true
B.	false
Answer» B. false

Discussion

410.	There exists a separate block consisting of various units to decode an instruction.
A.	true
B.	false
Answer» B. false

Discussion

411.	In a three BUS architecture, how many input and output ports are there?
A.	2 output and 2 input
B.	1 output and 2 input
C.	2 output and 1 input
D.	1 output and 1 input
Answer» D. 1 output and 1 input

Discussion

412.	In Â Â Â Â Â Â Â Â Â Â Â Â Â Â technology, the implementation of the register file is by using an array of memory locations.
A.	vlsi
B.	ansi
C.	isa
D.	asci
Answer» B. ansi

Discussion

413.	The small extremely fast, RAMâ€™s all called as
A.	cache
B.	heaps
C.	accumulators
D.	stacks
Answer» C. accumulators

Discussion

414.	Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â signal is used to show complete of memory operation.
A.	mfc
B.	wmfc
C.	cfc
D.	none of the mentioned
Answer» B. wmfc

Discussion

415.	The input and output of the registers are governed by
A.	transistors
B.	diodes
C.	gates
D.	switches
Answer» E.

Discussion

416.	Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â signal enables the processor to wait for the memory operation to complete.
A.	mfc
B.	tlb
C.	wmfc
D.	alb
Answer» D. alb

Discussion

417.	When two or more clock cycles are used to complete data transfer it is called as
A.	single phase clocking
B.	multi-phase clocking
C.	edge triggered clocking
D.	none of the mentioned
Answer» C. edge triggered clocking

Discussion

418.	The registers, ALU and the interconnecting path together are called as
A.	control path
B.	flow path
C.	data path
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

419.	The transparent register/s is/are
A.	y
B.	z
C.	temp
D.	all of the mentioned
Answer» E.

Discussion

420.	Which register in the processor is single directional?
A.	mar
B.	mdr
C.	pc
D.	temp
Answer» B. mdr

Discussion

421.	The PC gets incremented
A.	after the instruction decoding
B.	after the ir instruction gets executed
C.	after the fetch cycle
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

422.	Which register is connected to the MUX?
A.	y
B.	z
C.	r0
D.	temp
Answer» B. z

Discussion

423.	A common strategy for performance is making various functional units operate parallelly.
A.	true
B.	false
Answer» B. false

Discussion

424.	The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
A.	true
B.	false
Answer» B. false

Discussion

425.	The extra time needed to bring the data into memory in case of a miss is called as
A.	delay
B.	propagation time
C.	miss penalty
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

426.	If hit rates are well below 0.9, then theyâ€™re called as speedy computers.
A.	true
B.	false
Answer» C.

Discussion

427.	The CPU is also called as
A.	processor hub
B.	isp
C.	controller
D.	all of the mentioned
Answer» C. controller

Discussion

428.	In associative mapping during LRU, the counter of the new block is set to â€˜0â€™ and all the others are incremented by one, when Â Â Â Â Â Â Â Â Â Â Â occurs.
A.	delay
B.	miss
C.	hit
D.	delayed hit
Answer» C. hit

Discussion

429.	The number failed attempts to access memory, stated in the form of a fraction is called as
A.	hit rate
B.	miss rate
C.	failure rate
D.	delay rate
Answer» C. failure rate

Discussion

430.	The number successful accesses to memory stated as a fraction is called as
A.	hit rate
B.	miss rate
C.	success rate
D.	access rate
Answer» B. miss rate

Discussion

431.	In memory interleaving, the lower order bits of the address is used to
A.	get the data
B.	get the address of the module
C.	get the address of the data within the module
D.	none of the mentioned
Answer» C. get the address of the data within the module

Discussion

432.	In LRU, the referenced blocks counter is set toâ€™0â€² and that of the previous blocks are incremented by one and others remain same, in the case of
A.	hit
B.	miss
C.	delay
D.	none of the mentioned
Answer» B. miss

Discussion

433.	When consecutive memory locations are accessed only one module is accessed at a time.
A.	true
B.	false
Answer» B. false

Discussion

434.	The main memory is structured into modules each with its own address register called
A.	abr
B.	tlb
C.	pc
D.	ir
Answer» B. tlb

Discussion

435.	Data which is not up-to date is called as
A.	spoilt data
B.	stale data
C.	dirty data
D.	none of the mentioned
Answer» C. dirty data

Discussion

436.	The bit used to indicate whether the block was recently used or not is
A.	idol bit
B.	control bit
C.	reference bit
D.	dirty bit
Answer» E.

Discussion

437.	A control bit called Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â has to be provided to each block in set- associative.
A.	idol bit
B.	valid bit
C.	reference bit
D.	all of the mentioned
Answer» C. reference bit

Discussion

438.	In set-associative technique, the blocks are grouped into Â Â Â Â Â Â Â Â Â Â Â Â Â Â sets.
A.	4
B.	8
C.	12
D.	6
Answer» E.

Discussion

439.	The set-associative map technique is a combination of the direct and associative technique.
A.	true
B.	false
Answer» B. false

Discussion

440.	The technique of searching for a block by going through all the tags is
A.	linear search
B.	binary search
C.	associative search
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

441.	The associative mapping is costlier than direct mapping.
A.	true
B.	false
Answer» B. false

Discussion

442.	In associative mapping, in a 16 bit system the tag field has Â Â Â Â Â Â Â Â Â Â Â Â Â Â bits.
A.	12
B.	8
C.	9
D.	10
Answer» B. 8

Discussion

443.	In direct mapping the presence of the block in memory is checked with the help of block field.
A.	true
B.	false
Answer» C.

Discussion

444.	While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for
A.	tag
B.	block
C.	word
D.	id
Answer» B. block

Discussion

445.	During a write operation if the required block is not present in the cache then Â Â Â Â Â Â Â Â Â Â Â Â Â Â occurs.
A.	write latency
B.	write hit
C.	write delay
D.	write miss
Answer» E.

Discussion

446.	The only draw back of using the early start protocol is
A.	time delay
B.	complexity of circuit
C.	latency
D.	high miss rate
Answer» C. latency

Discussion

447.	In Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â protocol the information is directly written into the main memory.
A.	write through
B.	write back
C.	write first
D.	none of the mentioned
Answer» B. write back

Discussion

448.	The approach where the memory contents are transferred directly to the processor from the memory is called
A.	read-later
B.	read-through
C.	early-start
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

449.	The bit used to signify that the cache location is updated is
A.	dirty bit
B.	update bit
C.	reference bit
D.	flag bit
Answer» B. update bit

Discussion

450.	The write-through procedure is used
A.	to write onto the memory directly
B.	to write and read from memory simultaneously
C.	to write directly on the memory and the cache simultaneously
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

Explore topic-wise MCQs in Computer Science Engineering (CSE).

The disadvantage/s of the hardwired approach is

The benefit of using this approach is

BRâ€¦

What does the end instruction do?

The name hardwired came because the sequence of operations carried out is determined by the wiring.

Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â are the different type/s of generating control signals.

What does the hardwired control generator consist of?

The type of control signal is generated based on

There exists a separate block to increment the PC in multiple BUS organisation.

There exists a separate block consisting of various units to decode an instruction.

In a three BUS architecture, how many input and output ports are there?

In Â Â Â Â Â Â Â Â Â Â Â Â Â Â technology, the implementation of the register file is by using an array of memory locations.

The small extremely fast, RAMâ€™s all called as

Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â signal is used to show complete of memory operation.

The input and output of the registers are governed by

Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â signal enables the processor to wait for the memory operation to complete.

When two or more clock cycles are used to complete data transfer it is called as

The registers, ALU and the interconnecting path together are called as

The transparent register/s is/are

Which register in the processor is single directional?

The PC gets incremented

Which register is connected to the MUX?

A common strategy for performance is making various functional units operate parallelly.

The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.

The extra time needed to bring the data into memory in case of a miss is called as

If hit rates are well below 0.9, then theyâ€™re called as speedy computers.

The CPU is also called as

In associative mapping during LRU, the counter of the new block is set to â€˜0â€™ and all the others are incremented by one, when Â Â Â Â Â Â Â Â Â Â Â occurs.

The number failed attempts to access memory, stated in the form of a fraction is called as

The number successful accesses to memory stated as a fraction is called as

In memory interleaving, the lower order bits of the address is used to

In LRU, the referenced blocks counter is set toâ€™0â€² and that of the previous blocks are incremented by one and others remain same, in the case of

When consecutive memory locations are accessed only one module is accessed at a time.

The main memory is structured into modules each with its own address register called

Data which is not up-to date is called as

The bit used to indicate whether the block was recently used or not is

A control bit called Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â has to be provided to each block in set- associative.

In set-associative technique, the blocks are grouped into Â Â Â Â Â Â Â Â Â Â Â Â Â Â sets.

The set-associative map technique is a combination of the direct and associative technique.

The technique of searching for a block by going through all the tags is

The associative mapping is costlier than direct mapping.

In associative mapping, in a 16 bit system the tag field has Â Â Â Â Â Â Â Â Â Â Â Â Â Â bits.

In direct mapping the presence of the block in memory is checked with the help of block field.

While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for

During a write operation if the required block is not present in the cache then Â Â Â Â Â Â Â Â Â Â Â Â Â Â occurs.

The only draw back of using the early start protocol is

In Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â protocol the information is directly written into the main memory.

The approach where the memory contents are transferred directly to the processor from the memory is called

The bit used to signify that the cache location is updated is

The write-through procedure is used