MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 451. |
The copy-back protocol is used |
| A. | to copy the contents of the memory onto the cache |
| B. | to update the contents of the memory from the cache |
| C. | to remove the contents of the cache and push it on to the memory |
| D. | none of the mentioned |
| Answer» C. to remove the contents of the cache and push it on to the memory | |
| 452. |
The correspondence between the main memory blocks and those in the cache is given by |
| A. | hash function |
| B. | mapping function |
| C. | locale function |
| D. | assign function |
| Answer» C. locale function | |
| 453. |
The algorithm to remove and place new contents into the cache is called |
| A. | replacement algorithm |
| B. | renewal algorithm |
| C. | updation |
| D. | none of the mentioned |
| Answer» B. renewal algorithm | |
| 454. |
The spatial aspect of the locality of reference means |
| A. | that the recently executed instruction is executed again next |
| B. | that the recently executed won’t be executed again |
| C. | that the instruction executed will be executed at a later time |
| D. | that the instruction in close proximity of the instruction executed will be executed in future |
| Answer» E. | |
| 455. |
The temporal aspect of the locality of reference means |
| A. | that the recently executed instruction won’t be executed soon |
| B. | that the recently executed instruction is temporarily not referenced |
| C. | that the recently executed instruction will be executed soon again |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 456. |
The effectiveness of the cache memory is based on the property of |
| A. | locality of reference |
| B. | memory localisation |
| C. | memory size |
| D. | none of the mentioned |
| Answer» B. memory localisation | |
| 457. |
If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy. |
| A. | true |
| B. | false |
| Answer» C. | |
| 458. |
The reason for the implementation of the cache memory is |
| A. | to increase the internal memory of the system |
| B. | the difference in speeds of operation of the processor and memory |
| C. | to reduce the memory access and cycle time |
| D. | all of the mentioned |
| Answer» C. to reduce the memory access and cycle time | |
| 459. |
The last on the hierarchy scale of memory devices is |
| A. | main memory |
| B. | secondary memory |
| C. | tlb |
| D. | flash drives |
| Answer» C. tlb | |
| 460. |
In the memory hierarchy, as the speed of operation increases the memory size also increases. |
| A. | true |
| B. | false |
| Answer» C. | |
| 461. |
The next level of memory hierarchy after the L2 cache is |
| A. | secondary storage |
| B. | tlb |
| C. | main memory |
| D. | register |
| Answer» E. | |
| 462. |
The larger memory placed between the primary cache and the memory is called |
| A. | level 1 cache |
| B. | level 2 cache |
| C. | eeprom |
| D. | tlb |
| Answer» C. eeprom | |
| 463. |
The fastest data access is provided using |
| A. | caches |
| B. | dram’s |
| C. | sram’s |
| D. | registers |
| Answer» E. | |
| 464. |
The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called |
| A. | level 1 cache |
| B. | level 2 cache |
| C. | registers |
| D. | tlb |
| Answer» B. level 2 cache | |
| 465. |
To overcome the slow operating speeds of the secondary memory we make use of faster flash drives. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 466. |
The standard SRAM chips are costly as |
| A. | they use highly advanced micro- electronic devices |
| B. | they house 6 transistor per chip |
| C. | they require specially designed pcb’s |
| D. | none of the mentioned |
| Answer» C. they require specially designed pcb’s | |
| 467. |
The drawback of building a large memory with DRAM is |
| A. | the large cost factor |
| B. | the inefficient memory organisation |
| C. | the slow speed of operation |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 468. |
The reason for the fast operating speeds of the flash drives is |
| A. | the absence of any movable parts |
| B. | the integrated electronic hardware |
| C. | the improved bandwidth connection |
| D. | all of the mentioned |
| Answer» B. the integrated electronic hardware | |
| 469. |
The flash memory modules designed to replace the functioning of a hard disk is |
| A. | rimm |
| B. | flash drives |
| C. | fimm |
| D. | dimm |
| Answer» C. fimm | |
| 470. |
The flash memories find application in |
| A. | super computers |
| B. | mainframe systems |
| C. | distributed systems |
| D. | portable devices |
| Answer» E. | |
| 471. |
The memory devices which are similar to EEPROM but differ in the cost effectiveness is |
| A. | memory sticks |
| B. | blue-ray devices |
| C. | flash memory |
| D. | cmos |
| Answer» D. cmos | |
| 472. |
The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to be written. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 473. |
EEPROM stands for Electrically Erasable Programmable Read Only Memory. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 474. |
The disadvantage of the EPROM chip is |
| A. | the high cost factor |
| B. | the low efficiency |
| C. | the low speed of operation |
| D. | the need to remove the chip physically to reprogram it |
| Answer» E. | |
| 475. |
The contents of the EPROM are erased by |
| A. | overcharging the chip |
| B. | exposing the chip to uv rays |
| C. | exposing the chip to ir rays |
| D. | discharging the chip |
| Answer» C. exposing the chip to ir rays | |
| 476. |
The ROM chips are mainly used to store |
| A. | system files |
| B. | root directories |
| C. | boot files |
| D. | driver files |
| Answer» D. driver files | |
| 477. |
The difference between the EPROM and ROM circuitry is |
| A. | the usage of mosfet’s over transistors |
| B. | the usage of jfet’s over transistors |
| C. | the usage of an extra transistor |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 478. |
PROM stands for |
| A. | programmable read only memory |
| B. | pre-fed read only memory |
| C. | pre-required read only memory |
| D. | programmed read only memory |
| Answer» B. pre-fed read only memory | |
| 479. |
If the transistor gate is closed, then the ROM stores a value of 1. |
| A. | true |
| B. | false |
| Answer» C. | |
| 480. |
The RDRAM chips assembled into larger memory modules called |
| A. | rrim |
| B. | dimm |
| C. | simm |
| D. | all of the mentioned |
| Answer» B. dimm | |
| 481. |
A RAMBUS which has 18 data lines is called as |
| A. | extended rambus |
| B. | direct rambus |
| C. | multiple rambus |
| D. | indirect rambus |
| Answer» C. multiple rambus | |
| 482. |
The PROM is more effective than ROM chips in regard to |
| A. | cost |
| B. | memory management |
| C. | speed of operation |
| D. | both cost and speed of operation |
| Answer» E. | |
| 483. |
The RAMBUS requires specially designed memory chips similar to |
| A. | sram |
| B. | sdram |
| C. | dram |
| D. | ddrram |
| Answer» D. ddrram | |
| 484. |
The original design of the RAMBUS required for                   data lines. |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 9 |
| Answer» E. | |
| 485. |
The special communication used in RAMBUS are |
| A. | rambus channel |
| B. | d-link |
| C. | dial-up |
| D. | none of the mentioned |
| Answer» B. d-link | |
| 486. |
The type of signaling used in RAMBUS is |
| A. | clk signaling |
| B. | differential signaling |
| C. | integral signaling |
| D. | none of the mentioned |
| Answer» C. integral signaling | |
| 487. |
The data is transferred over the RAMBUS as |
| A. | packets |
| B. | blocks |
| C. | swing voltages |
| D. | bits |
| Answer» D. bits | |
| 488. |
The increase in operation speed is done by |
| A. | reducing the reference voltage |
| B. | increasing the clk frequency |
| C. | using enhanced hardware |
| D. | none of the mentioned |
| Answer» B. increasing the clk frequency | |
| 489. |
The key feature of the RAMBUS tech is |
| A. | greater memory utilisation |
| B. | efficiency |
| C. | speed of transfer |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 490. |
RAMBUS is better than the other memory chips in terms of |
| A. | efficiency |
| B. | speed of operation |
| C. | wider bandwidth |
| D. | all of the mentioned |
| Answer» C. wider bandwidth | |
| 491. |
When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 492. |
The RAS and CAS signals are provided by the |
| A. | mode register |
| B. | cs |
| C. | memory controller |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 493. |
The controller multiplexes the addresses after getting the            signal. |
| A. | intr |
| B. | ack |
| C. | reset |
| D. | request |
| Answer» E. | |
| 494. |
The address lines multiplexing is done using |
| A. | mmu |
| B. | memory controller unit |
| C. | page table |
| D. | overlay generator |
| Answer» C. page table | |
| 495. |
The higher order bits of the address are used to |
| A. | specify the row address |
| B. | specify the column address |
| C. | input the cs |
| D. | none of the mentioned |
| Answer» B. specify the column address | |
| 496. |
The less space consideration as lead to the development of                   (for large memories). |
| A. | simm’s |
| B. | dims’s |
| C. | sram’s |
| D. | both simm’s and dims’s |
| Answer» E. | |
| 497. |
To organise large memory chips we make use of |
| A. | integrated chips |
| B. | upgraded hardware |
| C. | memory modules |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 498. |
The SRAM’s are basically used as |
| A. | registers |
| B. | caches |
| C. | tlb |
| D. | buffer |
| Answer» C. tlb | |
| 499. |
The chip can be disabled or cut off from an external connection using |
| A. | chip select |
| B. | lock |
| C. | acpt |
| D. | reset |
| Answer» B. lock | |
| 500. |
The SDRAM performs operation on the |
| A. | rising edge of the clock |
| B. | falling edge of the clock |
| C. | middle state of the clock |
| D. | transition state of the clock |
| Answer» B. falling edge of the clock | |