MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 601. |
The 68000 uses                           method to access I/O devices buffers. |
| A. | memory mapped |
| B. | i/o mapped |
| C. | buffer mapped |
| D. | none of the mentioned |
| Answer» B. i/o mapped | |
| 602. |
The instructions in 68000 can deal with operands of three different sizes. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 603. |
Instructions which can handle any type of addressing mode are said to be |
| A. | omniscient |
| B. | orthogonal |
| C. | versatile |
| D. | none of the mentioned |
| Answer» C. versatile | |
| 604. |
The addresses generated by the 68000 is            bit. |
| A. | 32 |
| B. | 16 |
| C. | 24 |
| D. | 42 |
| Answer» D. 42 | |
| 605. |
The 68000 uses            address assignment. |
| A. | big endian |
| B. | little endian |
| C. | x-little endian |
| D. | x-big endian |
| Answer» B. little endian | |
| 606. |
When an operand is stored in a register it is |
| A. | stored in the lower order bits of the register |
| B. | stored in the higher order bits of the register |
| C. | stored in any of the bits at random |
| D. | none of the mentioned |
| Answer» B. stored in the higher order bits of the register | |
| 607. |
The 68000 has a max of how many data registers? |
| A. | 16 |
| B. | 20 |
| C. | 10 |
| D. | 8 |
| Answer» E. | |
| 608. |
Is 68000 computer Byte addressable? |
| A. | true |
| B. | false |
| Answer» B. false | |
| 609. |
The register in 68000 can contain up to            bits. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 64 |
| Answer» C. 16 | |
| 610. |
The general purpose registers are combined into a block called as |
| A. | register bank |
| B. | register case |
| C. | register file |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 611. |
Whenever a request to the page that is not present in the main memory is accessed               is triggered. |
| A. | interrupt |
| B. | request |
| C. | page fault |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 612. |
The word length in the 68000 computer is |
| A. | 32 bit |
| B. | 64 bit |
| C. | 16 bit |
| D. | 8 bit |
| Answer» D. 8 bit | |
| 613. |
           register is designated to point to the 68000 processor stack. |
| A. | a7 register |
| B. | b2 register |
| C. | there is no such designation |
| D. | any general purpose register is selected at random |
| Answer» B. b2 register | |
| 614. |
What does the RUN signal do? |
| A. | it causes the termination of a signal |
| B. | it causes a particular signal to perform its operation |
| C. | it causes a particular signal to end |
| D. | it increments the step counter by one |
| Answer» E. | |
| 615. |
The TLB is incorporated as part of the |
| A. | processor |
| B. | mmu |
| C. | disk |
| D. | ram |
| Answer» C. disk | |
| 616. |
When the page table is placed in the main memory, the                         is used to store the recently accessed pages. |
| A. | mmu |
| B. | tlb |
| C. | r0 |
| D. | table |
| Answer» C. r0 | |
| 617. |
If the page table is large then it is stored in |
| A. | processor |
| B. | main memory |
| C. | disk |
| D. | secondary storage |
| Answer» C. disk | |
| 618. |
The page table should be ideally situated within |
| A. | processor |
| B. | tlb |
| C. | mmu |
| D. | cache |
| Answer» D. cache | |
| 619. |
The bit used to store whether the page has been modified or not is called as |
| A. | dirty bit |
| B. | modify bit |
| C. | relocation bit |
| D. | none of the mentioned |
| Answer» B. modify bit | |
| 620. |
The bits used to indicate the status of the page in the memory is called |
| A. | control bits |
| B. | status bits |
| C. | progress bit |
| D. | none of the mentioned |
| Answer» B. status bits | |
| 621. |
The                 bit is used to indicate the validity of the page. |
| A. | valid bit |
| B. | invalid bit |
| C. | correct bit |
| D. | none of the mentioned |
| Answer» B. invalid bit | |
| 622. |
The starting address of the page table is stored in |
| A. | tlb |
| B. | r0 |
| C. | page table base register |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 623. |
The area in the main memory that can hold one page is called as |
| A. | page entry |
| B. | page frame |
| C. | frame |
| D. | block |
| Answer» C. frame | |
| 624. |
The lower order bits of the virtual address forms the |
| A. | page number |
| B. | frame number |
| C. | block number |
| D. | offset |
| Answer» E. | |
| 625. |
The higher order bits of the virtual address generated by the processor forms the |
| A. | table number |
| B. | frame number |
| C. | list number |
| D. | page number |
| Answer» E. | |
| 626. |
The cache bridges the speed gap between               and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 627. |
The pages size shouldn’t be too small, as this would lead to |
| A. | transfer errors |
| B. | increase in operation time |
| C. | increase in access time |
| D. | decrease in performance |
| Answer» D. decrease in performance | |
| 628. |
The page length shouldn’t be too long because |
| A. | it reduces the program efficiency |
| B. | it increases the access time |
| C. | it leads to wastage of memory |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 629. |
The virtual memory bridges the size and speed gap between                       and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» C. processor and ram | |
| 630. |
For converting a virtual address into the physical address, the programs are divided into |
| A. | pages |
| B. | frames |
| C. | segments |
| D. | blocks |
| Answer» B. frames | |
| 631. |
The memory allocated to each page is contiguous. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 632. |
Which of the architecture is power efficient? |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | iana |
| Answer» C. isa | |
| 633. |
In CISC architecture most of the complex instructions are stored in |
| A. | register |
| B. | diodes |
| C. | cmos |
| D. | transistors |
| Answer» E. | |
| 634. |
Pipe-lining is a unique feature of |
| A. | risc |
| B. | cisc |
| C. | isa |
| D. | iana |
| Answer» B. cisc | |
| 635. |
Both the CISC and RISC architectures have been developed to reduce the |
| A. | cost |
| B. | time delay |
| C. | semantic gap |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 636. |
The iconic feature of the RISC machine among the following is |
| A. | reduced number of addressing modes |
| B. | increased memory size |
| C. | having a branch delay slot |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 637. |
The RISC processor has a more complicated design than CISC. |
| A. | true |
| B. | false |
| Answer» C. | |
| 638. |
The Sun micro systems processors usually follow            architecture. |
| A. | cisc |
| B. | isa |
| C. | ultra sparc |
| D. | risc |
| Answer» E. | |
| 639. |
The computer architecture aimed at reducing the time of execution of instructions is |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | anna |
| Answer» C. isa | |
| 640. |
The CISC stands for |
| A. | computer instruction set compliment |
| B. | complete instruction set compliment |
| C. | computer indexed set components |
| D. | complex instruction set computer |
| Answer» E. | |
| 641. |
The commitment unit uses a queue called |
| A. | record buffer |
| B. | commitment buffer |
| C. | storage buffer |
| D. | none of the mentioned |
| Answer» B. commitment buffer | |
| 642. |
A special unit used to govern the out of order execution of the instructions is called as |
| A. | commitment unit |
| B. | temporal unit |
| C. | monitor |
| D. | supervisory unit |
| Answer» B. temporal unit | |
| 643. |
The step where in the results stored in the temporary register is transferred into the permanent register is called as |
| A. | final step |
| B. | commitment step |
| C. | last step |
| D. | inception step |
| Answer» C. last step | |
| 644. |
Since it uses the out of order mode of execution, the results are stored in |
| A. | buffers |
| B. | special memory locations |
| C. | temporary registers |
| D. | tlb |
| Answer» D. tlb | |
| 645. |
In super-scalar mode, all the similar instructions are grouped and executed together. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 646. |
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have |
| A. | exception handling |
| B. | imprecise exceptions |
| C. | error correction |
| D. | none of the mentioned |
| Answer» C. error correction | |
| 647. |
When the processor executes multiple instructions at a time it is said to use |
| A. | single issue |
| B. | multiplicity |
| C. | visualization |
| D. | multiple issues |
| Answer» E. | |
| 648. |
The throughput of a super scalar processor is |
| A. | less than 1 |
| B. | 1 |
| C. | more than 1 |
| D. | not known |
| Answer» D. not known | |
| 649. |
If a unit completes its task before the allotted time period, then |
| A. | special memory locations |
| B. | special purpose registers |
| C. | cache |
| D. | buffers |
| Answer» D. buffers | |
| 650. |
The               plays a very vital role in case of super scalar processors. |
| A. | compilers |
| B. | motherboard |
| C. | memory |
| D. | peripherals |
| Answer» B. motherboard | |