A half adder includes

neither OR nor XOR nor AND gate

Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion A): A code converter is a logic circuit whose inputs are bit patterns representing numbers in one code and whose outputs are the corresponding representation in a different code.Reason R): A sequential circuit performs this transformation by means of logic gates.

Both A) and R) are true and R) is the correct explanation of A)

Both A) and R) are true, but R) is not the correct explanation of A)

A combinational circuit is the one in which output depends on the

Present and the previous output

Present input combination and the previous output

Present input combination and the previous input combination

Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): A de-multiplexer cannot be used as a decoder.Reason (R): A de-multiplexer selects one of many outputs, whereas a decoder selects an output corresponding to the coded input.

Both A and R are individually true and R is the correct explanation of A

Both A and R are individually true but R is NOT the correct explanation of A

5 : 32 decoder circuit can be implemented with ______.

One 2 : 4 decoder and four 3 : 8 decoders

Consider three 4-variable functions f1, f2, and f3, which are expressed in sum-of-min terms asf1 = ∑ (0, 2, 5, 8, 14), f2 = ∑ (2, 3, 6, 8, 14, 15), f3 = ∑ (2, 7, 11, 14)For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:

∑ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)

249 + Mcqs in Combinational Logic Circuits in Digital Electronics Page 1 McqOptions

1.	A 4-bit adder has the following inputs: C = 0, A = 0, A = 1, A = 0, A = 1, B = 0, B = 1, B = 1, B = 1. The output will be ________.
A.	01100
B.	10101
C.	11000
D.	00011
Answer» D. 00011

Discussion

2.	The K-map in the figure below shows the correct implementation of the expression = + ( + ).
A.	True
B.	False
Answer» C.

Discussion

3.	The Boolean equation of the exclusive-NOR function is .
A.	True
B.	False
Answer» B. False

Discussion

4.	is in the form of a sum-of-products expression.
A.	True
B.	False
Answer» B. False

Discussion

5.	The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0
A.	True
B.	False
Answer» B. False

Discussion

6.	In an even-parity system, the following data will produce a parity bit = 1.data = 1010011
A.	True
B.	False
Answer» C.

Discussion

7.	The simplified form of .
A.	True
B.	False
Answer» B. False

Discussion

8.	The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0
A.	True
B.	False
Answer» C.

Discussion

9.	How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 300?
A.	1
B.	2
C.	3
D.	4
Answer» D. 4

Discussion

10.	The correct output for this XOR truth table is ________.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» E.

Discussion

11.	The Boolean equation for the exclusive-OR function is ________.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» E.

Discussion

12.	The Boolean equation ________ results from this Karnaugh map.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» B. [B].

Discussion

13.	The simplified form of is ________.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» E.

Discussion

14.	The equation ________ cannot be further simplified.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» B. [B].

Discussion

15.	Which of the following logic expressions represents the logic diagram shown?
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» E.

Discussion

16.	The simplest equation which implements the K-map shown below is:
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» B. [B].

Discussion

17.	A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» B. [B].

Discussion

18.	In the 4×1 multiplexer output F is given by F = A⊕B. Find the required input I3I2I1I0.
A.	1010
B.	0110
C.	1000
D.	1110
Answer» C. 1000

Discussion

19.	Minimum number of Half adders, Full adders, AND gates required to implement 2 × 3 multiplier is given as
A.	1, 2, 6
B.	1, 1, 6
C.	2, 2, 6
D.	2, 1, 6
Answer» E.

Discussion

20.	Match List - I with List-II and select the correct answer using the code given below the lists:List - IList - IIA) AND gate1) Boolean complementationB) OR gate2) Boolean addition C) NOT gate3) Boolean multiplication
A.	A - 3, B - 1, C - 2
B.	A - 1, B - 2, C - 3
C.	A - 3, B - 2, C - 1
D.	A - 1, B - 3, C - 2
Answer» D. A - 1, B - 3, C - 2

Discussion

21.	Based on the paragraph given below answer the following question:The traditional methods of combinational circuits involve simplification and realization using gates. Using these methods, complex functions have been integrated and are easily available in IC form. There is an attractive array of devices like a multiplexer, demultiplexer, decoders, comparators, parity generators/checkers, which significantly reduce IC package count there by reducing the system cost. The system design is greatly simplified because the laborious and time-consuming simplification methods are generally not required with these devices. This also improves the reliability of the system by reducing the number of external wired connections. But they have some limitations as well. Different memories like ROM, PROM can also be used to implement combinational circuits without much simplification.A logic circuit required for converting BCD Code to 7 segment Code is known as:
A.	Multiplexer
B.	Demultiplexer
C.	Decoder
D.	Encoder
Answer» D. Encoder

Discussion

22.	Consider the following circuit which uses a 2–to–1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is
A.	\(A \oplus B\)
B.	\(\overline {A + B}\)
C.	\(A + B\)
D.	\(\overline {A \oplus B} \)
Answer» E.

Discussion

23.	A combinational logic circuit which is used when it is desired to send data form two or more source through a single transmission line is known as
A.	encoder
B.	decoder
C.	multiplexer
D.	demultiplexer
Answer» D. demultiplexer

Discussion

24.	A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 is represented by 0001, …, 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and output as 1, if the digit is ≥ 5, and 0 otherwise. It only AND, OR and NOT gates may be used, what is the minimum number of gates required?
A.	4
B.	3
C.	2
D.	1
Answer» C. 2

Discussion

25.	7404 is a:
A.	Triple 3-input NAND gate
B.	Quad 2-input AND gate
C.	Hex inverter
D.	Quad 2-input NAND gate
Answer» D. Quad 2-input NAND gate

Discussion

26.	In the following truth table, V = 1 if and only if the input is valid.InputsOutputsD0D1D2D3X0X1V0000xx01000001x100011xx10101xxx1111 What function does the truth table represent?
A.	Priority encoder
B.	Decoder
C.	Multiplexer
D.	Demultiplexer
Answer» B. Decoder

Discussion

27.	A and B are the logical inputs and X is the logical output shown in the figure. The output X is related to A and B by
A.	X = A̅B + B̅A
B.	X = AB + B̅A
C.	X = AB + A̅B̅
D.	X = A̅B̅ + B̅A
Answer» D. X = A̅B̅ + B̅A

Discussion

28.	A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, and S2, (with S0 as the LSB) and Y̅0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A0 and A1) as shown in the figure. Din, S0, S1, and S2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
A.	S2, Din, S0, and S1
B.	S1, Din, S0, and S2
C.	Din, S0, S1, and S2
D.	Din, S2, S0, and S1
Answer» E.

Discussion

29.	In case of the parallel adder, the speed with which an addition can be performed is governed by the time required for the carries to propagate or ripple through all the stages of the adder. Which of the following statements are correct?(A) The method of speeding up the addition process is based on additional functions of full adder called carry generate and carry propagation.(B) The look-ahead carry adder speeds up the process by eliminating ripple carry dely.(C) The final sum output of the nth stage is given by \({S_n} = {P_n} \oplus {C_n}\) where \({P_n} = {A_n} \oplus {B_n}\)(D) The final carry output of nth stage is given by Cn+1 = Gn + Pn where Gn = An ⋅ BnChoose the correct answer from the options given below:(1) (A) and (B) only(2) (A) and (C) only(3) (A), (B) and (C) only(4) (B), (C) and (D) only
A.	1
B.	2
C.	3
D.	4
Answer» D. 4

Discussion

30.	A half adder includes
A.	a NAND gate with OR gate
B.	a AND gate with XOR gate
C.	only AND gate
D.	neither OR nor XOR nor AND gate
Answer» C. only AND gate

Discussion

31.	How many 3 × 8 line decoders with an enable input line are needed to construct a 6 × 64 line decoder without using any other logic gate?
A.	7
B.	8
C.	9
D.	10
Answer» D. 10

Discussion

32.	A 12-bit parallel subtractor needs how many Full Adders?
A.	14
B.	12
C.	18
D.	16
Answer» C. 18

Discussion

33.	Consider the circuit shown in the figure. The expression for the next state Q(t + 1) is
A.	xQ(t)
B.	x⊕ Q(t)
C.	xQ̅ (t)
D.	x ⊙ Q(t)
Answer» C. xQ̅ (t)

Discussion

34.	In NOR-NOR configuration, the minimum number of NOR gates needed to implement the switching function \(X + X\overline Y + X\overline Y Z\) is:
A.	5
B.	3
C.	2
D.	0
Answer» E.

Discussion

35.	In the following circuit, Y can be expressed as:
A.	Y = BC + A
B.	Y = C
C.	Y = AC’ + BC
D.	Y = B
Answer» E.

Discussion

36.	A 4 to 1 multiplexer to realize a Boolean function F (X, Y, Z) is shown in the figure below. The inputs Y and Z are connected to the selectors of the MUX (Y is more significant). The canonical sum-of-product expression for F (X, Y, Z) is
A.	∑m (2, 3, 4, 7)
B.	∑m (1, 3, 5, 7)
C.	∑m (0, 2, 4, 6)
D.	∑m (2, 3, 5, 6)
Answer» B. ∑m (1, 3, 5, 7)

Discussion

37.	Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion A): A code converter is a logic circuit whose inputs are bit patterns representing numbers in one code and whose outputs are the corresponding representation in a different code.Reason R): A sequential circuit performs this transformation by means of logic gates.
A.	Both A) and R) are true and R) is the correct explanation of A)
B.	Both A) and R) are true, but R) is not the correct explanation of A)
C.	is true, but R) is false
D.	is false, but R) is true
Answer» D. is false, but R) is true

Discussion

38.	A combinational circuit is the one in which output depends on the
A.	Input combination at that time
B.	Present and the previous output
C.	Present input combination and the previous output
D.	Present input combination and the previous input combination
Answer» B. Present and the previous output

Discussion

39.	Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): A de-multiplexer cannot be used as a decoder.Reason (R): A de-multiplexer selects one of many outputs, whereas a decoder selects an output corresponding to the coded input.
A.	Both A and R are individually true and R is the correct explanation of A
B.	Both A and R are individually true but R is NOT the correct explanation of A
C.	A is true but R is false
D.	A is false but R is true
Answer» E.

Discussion

40.	In the circuit shown in the figure, if
A.	Y = A B̅ + A̅ B
B.	Y = A + B
C.	Y = A̅ + B̅
D.	Y = A B
Answer» B. Y = A + B

Discussion

41.	Digital multiplexer is basically a combinational logic circuit to perform the operation
A.	AND-AND
B.	OR-OR
C.	AND-OR
D.	OR-AND
Answer» D. OR-AND

Discussion

42.	5 : 32 decoder circuit can be implemented with ______.
A.	One 2 : 4 decoder and four 3 : 8 decoders
B.	Four 3 : 8 decoders
C.	Two 3 : 8 decoders
D.	Eight 2 : 4 decoders
Answer» B. Four 3 : 8 decoders

Discussion

43.	Given two half adders, what extra 2-input gate is required to build a full adder?
A.	NOR gate
B.	XOR gate
C.	OR gate
D.	AND gate
Answer» D. AND gate

Discussion

44.	How many full adders are needed to construct an m - bit parallel adder
A.	m/2
B.	m
C.	m – 1
D.	m + 1
Answer» C. m – 1

Discussion

45.	Encoders are made by three __________ gates.
A.	AND
B.	OR
C.	NAND
D.	XOR
Answer» C. NAND

Discussion

46.	A bulb in a staircases has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by and one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles
A.	AND gate
B.	OR gate
C.	NAND gate
D.	XOR gate
Answer» E.

Discussion

47.	A four-variable boolean function is realized using 4 × 1 multiplexers as shown in the figure.The minimized expression for F(U, V, W, X) is
A.	(UV + U̅V̅) W̅
B.	(UV + U̅V̅) (W̅X̅ + W̅X)
C.	(UV̅ + U̅V) W̅
D.	(UV̅ + U̅V) (W̅X̅ + W̅X)
Answer» D. (UV̅ + U̅V) (W̅X̅ + W̅X)

Discussion

48.	AND gate EXOR gate combination is ____
A.	both full and half adder.
B.	full adder
C.	half adder
D.	flip flop
Answer» D. flip flop

Discussion

49.	Consider the following statements:1. A multiplexer is analogous to a rotary switch.2. A decoder is a combinational logic circuit that converts binary information from 'n' input lines to a maximum of 2n distinct elements at the output.3. The Boolean expression for the output difference 'D' from a null subtractor is exactly the same as the output sum 'S' from a full adder.Which of the above statements is/are correct?
A.	2 and 4 only
B.	4 only
C.	1 and 3 only
D.	1, 2 and 3
Answer» B. 4 only

Discussion

50.	Consider three 4-variable functions f1, f2, and f3, which are expressed in sum-of-min terms asf1 = ∑ (0, 2, 5, 8, 14), f2 = ∑ (2, 3, 6, 8, 14, 15), f3 = ∑ (2, 7, 11, 14)For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:
A.	∑ (7, 8, 11)
B.	∑ (2, 7, 8, 11, 14)
C.	∑ (2, 14)
D.	∑ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)
Answer» B. ∑ (2, 7, 8, 11, 14)

Discussion

Explore topic-wise MCQs in Digital Electronics.

A 4-bit adder has the following inputs: C = 0, A = 0, A = 1, A = 0, A = 1, B = 0, B = 1, B = 1, B = 1. The output will be ________.

The K-map in the figure below shows the correct implementation of the expression = + ( + ).

The Boolean equation of the exclusive-NOR function is .

is in the form of a sum-of-products expression.

The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0

In an even-parity system, the following data will produce a parity bit = 1.data = 1010011

The simplified form of .

The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0

How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 300?

The correct output for this XOR truth table is ________.

The Boolean equation for the exclusive-OR function is ________.

The Boolean equation ________ results from this Karnaugh map.

The simplified form of is ________.

The equation ________ cannot be further simplified.

Which of the following logic expressions represents the logic diagram shown?

The simplest equation which implements the K-map shown below is:

A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?

In the 4×1 multiplexer output F is given by F = A⊕B. Find the required input I3I2I1I0.

Minimum number of Half adders, Full adders, AND gates required to implement 2 × 3 multiplier is given as

Match List - I with List-II and select the correct answer using the code given below the lists:List - IList - IIA) AND gate1) Boolean complementationB) OR gate2) Boolean addition C) NOT gate3) Boolean multiplication

Consider the following circuit which uses a 2–to–1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is

A combinational logic circuit which is used when it is desired to send data form two or more source through a single transmission line is known as

7404 is a:

In the following truth table, V = 1 if and only if the input is valid.InputsOutputsD0D1D2D3X0X1V0000xx01000001x100011xx10101xxx1111 What function does the truth table represent?

A and B are the logical inputs and X is the logical output shown in the figure. The output X is related to A and B by

A half adder includes

How many 3 × 8 line decoders with an enable input line are needed to construct a 6 × 64 line decoder without using any other logic gate?

A 12-bit parallel subtractor needs how many Full Adders?

Consider the circuit shown in the figure. The expression for the next state Q(t + 1) is

In NOR-NOR configuration, the minimum number of NOR gates needed to implement the switching function \(X + X\overline Y + X\overline Y Z\) is:

In the following circuit, Y can be expressed as:

A 4 to 1 multiplexer to realize a Boolean function F (X, Y, Z) is shown in the figure below. The inputs Y and Z are connected to the selectors of the MUX (Y is more significant). The canonical sum-of-product expression for F (X, Y, Z) is

A combinational circuit is the one in which output depends on the

In the circuit shown in the figure, if

Digital multiplexer is basically a combinational logic circuit to perform the operation

5 : 32 decoder circuit can be implemented with ______.

Given two half adders, what extra 2-input gate is required to build a full adder?

How many full adders are needed to construct an m - bit parallel adder

Encoders are made by three __________ gates.

A bulb in a staircases has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by and one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

A four-variable boolean function is realized using 4 × 1 multiplexers as shown in the figure.The minimized expression for F(U, V, W, X) is

AND gate EXOR gate combination is ____

Consider three 4-variable functions f1, f2, and f3, which are expressed in sum-of-min terms asf1 = ∑ (0, 2, 5, 8, 14), f2 = ∑ (2, 3, 6, 8, 14, 15), f3 = ∑ (2, 7, 11, 14)For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as: