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This section includes 40 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
1. |
There are four different logic level ranges for TTL and CMOS: V, V, V, and V. |
A. | True |
B. | False |
Answer» B. False | |
2. |
A TTL NAND gate with I of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink? |
A. | –12.8 mA |
B. | –8 mA |
C. | –1.6 mA |
D. | –25.6 mA |
Answer» B. –8 mA | |
3. |
If I is specified as 1.1 mA when V is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (P) of the gate is ________. |
A. | 5.5 mW |
B. | 5.5 W |
C. | 5 mW |
D. | 1.1 mW |
Answer» B. 5.5 W | |
4. |
A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink? |
A. | –12.8 mA |
B. | –8 mA |
C. | –1.6 mA |
D. | –25.6 mA |
Answer» B. –8 mA | |
5. |
A certain gate draws 1.8 A when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)? |
A. | 2.55 W |
B. | 1.27 W |
C. | 12.75 W |
D. | 5 W |
Answer» D. 5 W | |
6. |
Power dissipation is a measure of a circuit's noise immunity. |
A. | 1 |
B. | |
Answer» C. | |
7. |
Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in CMOS circuits. |
A. | 1 |
B. | |
Answer» B. | |
8. |
There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH. |
A. | 1 |
B. | |
Answer» B. | |
9. |
The total sink current decreases with an increase in each load gate input. |
A. | 1 |
B. | |
Answer» C. | |
10. |
An open-collector output requires ________. |
A. | a pull-down resistor |
B. | a pull-up resistor |
C. | no output resistor |
D. | an output resistor |
Answer» C. no output resistor | |
11. |
A certain gate draws 1.8 A when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)? |
A. | 2.55 W |
B. | 1.27 W |
C. | 12.75 W |
D. | 5 W |
Answer» D. 5 W | |
12. |
A TTL NAND gate with IIH(max) of 40 A per input drives ten TTL inputs. How much current does the drive output source? |
A. | 40 A |
B. | 200 A |
C. | 400 A |
D. | 800 A |
Answer» D. 800 A | |
13. |
The nominal value of the dc supply voltage for TTL and CMOS is ________. |
A. | +3 V |
B. | +5 V |
C. | +9 V |
D. | +12 V |
Answer» C. +9 V | |
14. |
The greater the propagation delay, the higher the maximum frequency. |
A. | 1 |
B. | |
Answer» C. | |
15. |
One output structure of a TTL gate is often referred to as a ________. |
A. | totem-pole arrangement |
B. | diode arrangement |
C. | JBT arrangement |
D. | base, emitter, collector arrangement |
Answer» B. diode arrangement | |
16. |
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________. |
A. | 5.5 mW |
B. | 5.5 W |
C. | 5 mW |
D. | 1.1 mW |
Answer» B. 5.5 W | |
17. |
TTL is alive and well, particularly in ________. |
A. | industrial applications |
B. | educational applications |
C. | military applications |
D. | commercial applications |
Answer» C. military applications | |
18. |
Which factor does not affect CMOS loading? |
A. | Charging time associated with the output resistance of the driving gate |
B. | Discharging time associated with the output resistance of the driving gate |
C. | Output capacitance of the load gates |
D. | Input capacitance of the load gates |
Answer» D. Input capacitance of the load gates | |
19. |
ECL IC technology is faster than TTL technology. |
A. | 1 |
B. | |
Answer» B. | |
20. |
Which is not part of emitter-coupled logic (ECL)? |
A. | Differential amplifier |
B. | Bias circuit |
C. | Emitter-follower circuit |
D. | Totem-pole circuit |
Answer» E. | |
21. |
A pull-down resistor must be used with open-collector TTL circuits. |
A. | 1 |
B. | |
C. | 1 |
D. | |
Answer» C. 1 | |
22. |
Which equation is correct? |
A. | VNL = VIL(max) + VOL(max) |
B. | VNH = VOH(min) + VIH(min) |
C. | VNL = VOH(min) – VIH(min) |
D. | VNH = VOH(min) – VIH(min) |
Answer» E. | |
23. |
Most TTL logic used today is some form of ________. |
A. | Schottky TTL |
B. | tristate TTL |
C. | low-power TTL |
D. | open-collector TTL |
Answer» B. tristate TTL | |
24. |
CMOS is a more dominant IC technology than TTL. |
A. | 1 |
B. | |
Answer» B. | |
25. |
Which logic family combines the advantages of CMOS and TTL? |
A. | BiCMOS |
B. | TTL/CMOS |
C. | ECL |
D. | TTL/MOS |
Answer» B. TTL/CMOS | |
26. |
A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)), ________. |
A. | 16 mA |
B. | 20 mA |
C. | 16 A |
D. | 20 A |
Answer» B. 20 mA | |
27. |
Which is not a precaution for handling CMOS? |
A. | Devices should be placed with pins down on a grounded surface, such as a metal plate. |
B. | All tools, test equipment, and metal workbenches should be earth grounded. |
C. | CMOS devices should not be inserted into sockets or PC boards with the power on. |
D. | Wear wool clothes at all times. |
Answer» E. | |
28. |
Which is not an output state for tristate logic? |
A. | HIGH |
B. | LOW |
C. | High-Z |
D. | Low-Z |
Answer» E. | |
29. |
Unused TTL inputs should be tied LOW. |
A. | 1 |
B. | |
Answer» C. | |
30. |
A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink? |
A. | –12.8 mA |
B. | –8 mA |
C. | –1.6 mA |
D. | –25.6 mA |
Answer» B. ‚Äì8 mA | |
31. |
In a TTL circuit, if an excessive number of load gate inputs are connected, ________. |
A. | VOH(min) drops below VOH |
B. | VOH drops below VOH(min) |
C. | VOH exceeds VOH(min) |
D. | VOH and VOH(min) are unaffected |
Answer» C. VOH exceeds VOH(min) | |
32. |
PMOS and NMOS circuits are used largely in ________. |
A. | MSI functions |
B. | LSI functions |
C. | diode functions |
D. | TTL functions |
Answer» C. diode functions | |
33. |
It is best not to leave unused TTL inputs unconnected (open) because of TTL's ________. |
A. | noise sensitivity |
B. | low-current requirement |
C. | open-collector outputs |
D. | tristate construction |
Answer» B. low-current requirement | |
34. |
For a CMOS gate, which is the best speed-power product? |
A. | 1.4 pJ |
B. | 1.6 pJ |
C. | 2.4 pJ |
D. | 3.3 pJ |
Answer» B. 1.6 pJ | |
35. |
The active switching element used in all TTL circuits is the ________. |
A. | bipolar junction transistor (BJT) |
B. | field-effect transistor (FET) |
C. | metal-oxide semiconductor field-effect transistor (MOSFET) |
D. | unijunction transistor (UJ) |
Answer» B. field-effect transistor (FET) | |
36. |
The speed-power product provides a basis for the comparison of logic circuits when power dissipation and propagation delay are important considerations in the selection of the type of logic to be used. |
A. | 1 |
B. | |
C. | 1 |
D. | |
Answer» B. | |
37. |
The greater the propagation delay, the ________. |
A. | lower the maximum frequency |
B. | higher the maximum frequency |
C. | maximum frequency is unaffected |
D. | minimum frequency is unaffected |
Answer» B. higher the maximum frequency | |
38. |
Which transistor element is used in CMOS logic? |
A. | FET |
B. | MOSFET |
C. | Bipolar |
D. | Unijunction |
Answer» C. Bipolar | |
39. |
An open-drain gate is the CMOS counterpart of ________. |
A. | an open-collector TTL gate |
B. | a tristate TTL gate |
C. | a bipolar junction transistor |
D. | an emitter-coupled logic gate |
Answer» B. a tristate TTL gate | |
40. |
Which is not a MOSFET terminal? |
A. | Gate |
B. | Drain |
C. | Source |
D. | Base |
Answer» E. | |