MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 20 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
A semiconductor RAM has a 12-bit address register and an 8-bit data register. The total number of bits in the memory is |
| A. | 256 bits |
| B. | 4,096 bits |
| C. | 32,768 bits |
| D. | 10,48,576 bits |
| Answer» D. 10,48,576 bits | |
| 2. |
Addressing of a 32K × 16 memory is realized using a single decoder. The minimum number of AND gates required for the decoder is |
| A. | 215 |
| B. | 219 |
| C. | 232 |
| D. | 28 |
| Answer» B. 219 | |
| 3. |
An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figureThe interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines \({E_1},{\bar E_2},{\bar E_3}\). The address of the device is |
| A. | \({\left( {50} \right)_H}\) |
| B. | \({\left( {5000} \right)_H}\) |
| C. | \({\left( {A0} \right)_H}\) |
| D. | \({\left( {A000} \right)_H}\) |
| Answer» C. \({\left( {A0} \right)_H}\) | |
| 4. |
In a DRAM, |
| A. | periodic refreshing is not required |
| B. | information is stored in a capacitor |
| C. | information is stored in a latch |
| D. | both read and write operations can be performed simultaneously |
| Answer» C. information is stored in a latch | |
| 5. |
Consider the following statements comparing static RAM with dynamic RAM:In static RAM typical cell requires more number of transistors than the dynamic RAM.Power consumption per bit of static RAM is less than that of dynamic RAM.Dynamic RAM is less expensive than the static RAM.Which of the above statements are correct? |
| A. | 1, 2 and 3 |
| B. | 1 and 2 only |
| C. | 2 and 3 only |
| D. | 1 and 3 only |
| Answer» E. | |
| 6. |
How many address inputs are required to access 256 Bytes memory? |
| A. | 256 |
| B. | 2 |
| C. | 8 |
| D. | 16 |
| Answer» D. 16 | |
| 7. |
An 8 Kbyte ROM with an active low Chip Select input\(\left( {\overline {{\rm{CS}}} } \right)\) is to be used in an 8085 microprocessor-based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as |
| A. | A15 + A14 + (A 13 . A12 + A̅13 . A̅ 12) |
| B. | A15 . A14 . (A13 + A12) |
| C. | A̅15 . A̅ 14 . (A 13 . A̅12 + A̅13 . A12) |
| D. | A̅15 + A̅14 + (A13 . A12) |
| Answer» B. A15 . A14 . (A13 + A12) | |
| 8. |
Downloading means |
| A. | Transferring programs from a programming device to a PLC |
| B. | Transferring programs from one PLC to another PLC |
| C. | Transferring programs from memory to PLC's CPU |
| D. | Transferring program from output device to PLC |
| Answer» B. Transferring programs from one PLC to another PLC | |
| 9. |
A ROM is used to store the table for multiplication of two 8 bit unsigned integer ,the size of ROM required is |
| A. | 256x16 |
| B. | 16K x 16 |
| C. | 64Kx8 |
| D. | 256X8 |
| Answer» C. 64Kx8 | |
| 10. |
In microprocessor based systems DMA facility is required to increase the speed of data transfer between the: |
| A. | Microprocessor and the I/O devices |
| B. | Microprocessor and the memory |
| C. | Memory and the I/O devices |
| D. | Memory and the reliability system |
| Answer» D. Memory and the reliability system | |
| 11. |
A programmable logic array (PLA) is shown in the figure.The Boolean function F implemented is |
| A. | \(\bar P\bar QR + \bar PQR + P\bar Q\bar R\) |
| B. | \(\left( {\bar P + \bar Q + R} \right)\left( {\bar P + Q + R} \right)\left( {P + \bar Q + \bar R} \right)\) |
| C. | \(\bar P\bar QR + \bar PQR + P\bar QR\) |
| D. | \(\left( {\bar P + \bar Q + R} \right)\left( {\bar P + Q + R} \right)\left( {P + \bar Q + R} \right)\) |
| Answer» D. \(\left( {\bar P + \bar Q + R} \right)\left( {\bar P + Q + R} \right)\left( {P + \bar Q + R} \right)\) | |
| 12. |
Consider a memory chip with 1024 bytes storage connected to a 8085 chip address lines (or any microprocessor with 16 address lines) as above. What is the range of memory address? |
| A. | 0000 H to 03 FFH |
| B. | 1000 H to 13 FFH |
| C. | F000 H to F3FFH |
| D. | 0000 H to FFFFH |
| Answer» B. 1000 H to 13 FFH | |
| 13. |
Programmable logic array has |
| A. | Fixed OR plane followed by a programmable AND gate |
| B. | Fixed AND plane followed by a programmable OR gate |
| C. | Programmable OR gate followed by a fixed AND gate |
| D. | Programmable AND gate followed by a programmable OR gate |
| Answer» E. | |
| 14. |
PLA consists of _____. |
| A. | Programmable AND and fixed OR arrays |
| B. | Programmable AND and programmable OR arrays |
| C. | Fixed AND and Programmable OR arrays |
| D. | Fixed AND and Fixed OR arrays |
| Answer» C. Fixed AND and Programmable OR arrays | |
| 15. |
Identify the characteristic feature of random access memory |
| A. | It is a serial access memory |
| B. | Data can be read from or written into any of the memory location regardless of the order in which they are arranged |
| C. | All memory locations can be accessed with the same speed |
| D. | Both (2) and (3) |
| Answer» E. | |
| 16. |
A 1 Kbyte memory module has to be interfaced with an 8-bit microprocessor that has 16 address lines. The address lines A0 to A9 of the processor are connected to the corresponding address lines fo the memory module. The active low chip select \(\overline {CS}\) of the memory module is connected to the y5 output of a 3 to 8 decoder with active low outputs. S0, S1, and S2 are the input lines to the decoder, with S2 as the MSB. The decoder has one active low \({\overline {EN} _1}\) and one active high EN2 enable lines as shown below. The address range(s) that gets mapped onto this memory module is (are) |
| A. | 3000H to 33FFH and E000H to E3FFH |
| B. | 1400H to 17FFH |
| C. | 5300H to 53FFH and A300H to A3FFH |
| D. | 5800H to 5BFFH and D800H to DBFFH |
| Answer» E. | |
| 17. |
A single unit which is composed of small group of bits is known as- |
| A. | Bug |
| B. | Bit |
| C. | Byte |
| D. | Flag |
| Answer» D. Flag | |
| 18. |
Both EPROM and EEPROM are |
| A. | Sequential access memory |
| B. | Random access memory |
| C. | Volatile memory |
| D. | Destructive memory |
| Answer» C. Volatile memory | |
| 19. |
Match List I with List IIList I(Interrupt)List II(ROM location (Hex))(a) Reset(i) 001B(b) External hardware int. 0 (INT0)(ii) 0003(c) Timer 0 interrupt (TF0)(iii) 000B(d) Timer 1 interrupt (TF1)(iv) 0000 Choose the correct answer from the options given below: |
| A. | (a) - (iv), (b) - (ii), (c) - (iii), (d) - (i) |
| B. | (a) - (iv), (b) - (iii), (c) - (ii), (d) - (i) |
| C. | (a) - (iii), (b) - (ii), (c) - (iv), (d) - (i) |
| D. | (a) - (i), (b) - (ii), (c) - (iii), (d) - (iv) |
| Answer» B. (a) - (iv), (b) - (iii), (c) - (ii), (d) - (i) | |
| 20. |
A 2 × 2 ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to Dij (where i = 0 or 1 and j = 0 or 1) stored in the ROM? |
| A. | \(\left[ {\begin{array}{*{20}{c}}1&0\\0&1\end{array}} \right]\) |
| B. | \(\left[ {\begin{array}{*{20}{c}}0&1\\1&0\end{array}} \right]\) |
| C. | \(\left[ {\begin{array}{*{20}{c}}1&0\\1&0\end{array}} \right]\) |
| D. | \(\left[ {\begin{array}{*{20}{c}}1&1\\0&1\end{array}} \right]\) |
| Answer» B. \(\left[ {\begin{array}{*{20}{c}}0&1\\1&0\end{array}} \right]\) | |