MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 26 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
One example of the use of an S-R flip-flop is as a(n) _________. |
| A. | racer |
| B. | binary storage register |
| C. | astable oscillator |
| D. | transition pulse generator |
| Answer» C. astable oscillator | |
| 2. |
When using master-slave flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 3. |
For an S-R flip-flop to be SET or RESET, the respective input must be __________. |
| A. | LOW |
| B. | HIGH |
| C. | installed with steering diodes |
| D. | in parallel with a limiting resistor |
| Answer» C. installed with steering diodes | |
| 4. |
If an input is activated by a signal transition, it is _____________. |
| A. | edge-triggered |
| B. | toggle-triggered |
| C. | clock-triggered |
| D. | noise-triggered |
| Answer» B. toggle-triggered | |
| 5. |
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the _____________________. |
| A. | inverted, positive clock edge |
| B. | quiescent, negative clock edge |
| C. | opposite, active clock edge |
| D. | reset, synchronous clock edge |
| Answer» D. reset, synchronous clock edge | |
| 6. |
A D-type flip-flop is constructed by connecting an inverter between the Set and Clock terminals. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 7. |
When the S and the R inputs are both HIGH the output of an S-R NOR latch will be unpredictable. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 8. |
An astable multivibrator is a circuit that: |
| A. | has two stable states |
| B. | is free-running |
| C. | produces a continuous output signal |
| D. | is free-running and produces a continuous output signal |
| Answer» D. is free-running and produces a continuous output signal | |
| 9. |
Edge-triggered flip-flops must have _________. |
| A. | very fast response times |
| B. | at least two inputs to handle rising and falling edges |
| C. | a positive-transition pulse generator |
| D. | a negative-transition pulse generator |
| Answer» D. a negative-transition pulse generator | |
| 10. |
The S-R, D-type, and J-K flip-flops are all examples of _________________. |
| A. | astable multivibrators |
| B. | bistable multivibrators |
| C. | monostable multivibrators |
| D. | tristable multivibrators |
| Answer» C. monostable multivibrators | |
| 11. |
The equation for the output frequency of a 555 timer operating in the astable mode is: . What value of C1 will be required if R1 = 1 k, R2 = 1 k, and f = 1 kHz? |
| A. | 0.33 F |
| B. | 0.48 F |
| C. | 480 F |
| D. | 33 nF |
| Answer» C. 480 F | |
| 12. |
J-K flip-flops are often used as switch debouncers. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 13. |
Pulse-triggered flip-flops are also called _________ flip-flops. |
| A. | master-slave |
| B. | postponed |
| C. | level |
| D. | edge |
| Answer» B. postponed | |
| 14. |
The J-K flip-flop eliminates the RACE state when both the J and K inputs are HIGH. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 15. |
An S-R flip-flop can be triggered by ______, ______, or ________. |
| A. | HIGHs, LOWs, PRESETs |
| B. | edges, levels, pulses |
| C. | HIGHs, LOWs, CLEARs |
| D. | SETs, RESETs, HIGHs |
| Answer» C. HIGHs, LOWs, CLEARs | |
| 16. |
The 555 timer can be used in either the bistable mode or the monostable mode. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 17. |
If both inputs of an S-R NAND latch are LOW, what will happen to the output? |
| A. | The output would become unpredictable. |
| B. | The output will toggle. |
| C. | The output will reset. |
| D. | No change will occur in the output. |
| Answer» B. The output will toggle. | |
| 18. |
Which of the following describes the operation of a positive edge-triggered D-type flip-flop? |
| A. | If both inputs are HIGH, the output will toggle. |
| B. | The output will follow the input on the leading edge of the clock. |
| C. | When both inputs are LOW, an invalid state exists. |
| D. | The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock. |
| Answer» C. When both inputs are LOW, an invalid state exists. | |
| 19. |
An S-R NAND latch with both of its inputs LOW has an output that is _____________. |
| A. | unpredictable |
| B. | floating |
| C. | HIGH |
| D. | LOW |
| Answer» B. floating | |
| 20. |
A one-shot is a special type of multivibrator, which must be triggered to produce each output pulse. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 21. |
The truth table for an S-R flip-flop has how many VALID entries? |
| A. | 3 |
| B. | 1 |
| C. | 4 |
| D. | 2 |
| Answer» B. 1 | |
| 22. |
The 555 timer can be used in which of the following configurations? |
| A. | astable, monostable |
| B. | monostable, bistable |
| C. | astable, toggled |
| D. | bistable, tristable |
| Answer» B. monostable, bistable | |
| 23. |
A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms. |
| A. | 3 |
| B. | 7 |
| C. | 10 |
| D. | 13 |
| Answer» E. | |
| 24. |
When both inputs of a J-K flip-flop cycle, the output will: |
| A. | be invalid |
| B. | not change |
| C. | change |
| D. | toggle |
| Answer» C. change | |
| 25. |
A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates? |
| A. | AND or OR gates |
| B. | XOR or XNOR gates |
| C. | NOR or NAND gates |
| D. | AND or NOR gates |
| Answer» D. AND or NOR gates | |
| 26. |
Which of the following is correct for a gated D-type flip-flop? |
| A. | The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. |
| B. | The output complement follows the input when enabled. |
| C. | Only one of the inputs can be HIGH at a time. |
| D. | The output toggles if one of the inputs is held HIGH. |
| Answer» B. The output complement follows the input when enabled. | |