Explore topic-wise MCQs in Engineering.

The major structures in the MAX7000S are the ________ and ________.

The field programmable logic array was the first ________ programmable logic device.

In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

SPLD is a program language used by PLD software.

CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).

In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.

15₁₀ = 1111₂ = F₁₆ = 00010101 BCD

A type of shift register that requires access to the Q outputs of all stages is ________.

The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.

When the analog input to a tracking A/D converter is at a constant level, the digital output will oscillate.

To be useful, A/D or D/A converters must have meaningful representation of the analog quantity and a digital representation and the digital quantity as an analog representation.

A sample-and-hold circuit is used in D/A conversion.

The output of an analog-to-digital converter is a voltage level.

The digit bus and display bus are each just a common set of conductors shared by the digit storage registers and display segments.

A light bulb and a switch are examples of an analog circuit.

When a DAC output shows a deviation of the measured step size from the ideal step size, this error is called nonlinearity.

In a digital storage scope, when memory is full, the next data point is lost.

The basic comparator evaluates two binary strings bit by bit and always outputs a 1.

The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

A 2-input gate that can be used to pass a digital waveform unchanged at certain times and inverted at other times is a(n) ________.

The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?

A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.

PMOS and NMOS are commonly used for small memories and microprocessors.

Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.

A CPLD is basically a simplified PLD.

The GAL16V8 has 32 input variables.

Xilinx software uses triangular symbols called buffers to define pins as input or output.

LUT is an acronym for look-up table.

A PAL uses a programmable OR array followed by a fixed AND array.

The SRAM technology is volatile.

The architecture of a PAL differs slightly from that of a PROM.

The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.

The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).

All I/O pins in the MAX7000S family have a tristate buffer.

Antifuse devices are volatile.

The GAL16V8 has eight dedicated input pins.

In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.

The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.

With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.

The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.

The Altera FLEX10K family uses a look-up table (LUT) architecture.

PLDs cannot meet all the possible requirements of complex digital circuitry.

The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.

In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.

A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.

The schematic editor allows you to connect with predefined logic symbols.

All inputs to the MAX7000S device and all macrocell outputs feed the PIA.

Sum-of-products is two or more product terms that are NANDed together.

Most complex digital designs include a mix of different hardware categories.