Explore topic-wise MCQs in Engineering.

An Altera FLEX10K device uses a(n) ________ architecture.

Generally, PLDs can be described as being one of four different types.

The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with flash being most common.

In ECL, the HIGH and LOW levels are determined by which transistor in a differential amplifier is conducting more.

Propagation delay in TTL is due to slow switching speeds.

In TTL the noise margin is between 0.8 V and 0.4 V.

The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.

A decimal fraction can be converted to binary by using the repeated division-by-2 method.

The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.

Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

Schematic capture is a process performed by PLD software.

An expensive form of programmable logic is SPLD.

The FPLA has a programmable AND array and a programmable OR array.

Using a hardware solution for your digital system design is always faster than a software solution.

Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.

The hard core portions of FPGAs are reprogrammable in the field.

A GAL22V10 ________.

Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.

The Boolean expression AB + CD is an example of ________.

In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.

The SPLD classification includes the ________ PLD devices.

The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.

The EPM 7128S is a(n) ________ device.

________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.

Full custom ICs can operate at ________ and require the ________.

A macrocell is ________.

Using a hardware solution for a digital system is always ________ than a software solution.

The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.

The final step in a design flow in which the logic design is implemented in the target device is called ________.

A method for the automated testing of printed circuit boards is called a(n) ________.

In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.

The process or sequence of all operations carried out to ultimately program a target device is called the ________.

In the GAL16V8, the ________ controls the tristate buffer's enable input.

All inputs to the MAX7000S device and all macrocell outputs feed the ________.

A ring counter is a register in which a certain pattern of 1s and 0s is continuously outputted in parallel.

In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.

An application program in the development software package that controls the operation of the software is called a ________.

Bidirectional means having two states.

Eight states are in an 8-bit Johnson counter sequence.

A stage is two storage elements in a register.

When is LOW, the data are shifted one bit per clock pulse.

The flexibility of the GAL16V8 is in its ________.

Design costs for standard cell ASICs are ________ those for MPGAs.

A stepper motor makes its rotation in smooth continuous motion.

A universal shift register has both serial and parallel input and output capacity.

The storage capacity of a register makes it an important type of memory.

The 74194 4-bit bidirectional universal shift register has a wide range of applications.

In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.

Practically every possible load, shift, and conversion operation is available in a shift register IC.

Adding an odd-parity bit to ASCII hex code 2B results in 10101011.