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MCQOPTIONS
This section includes 2291 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 851. |
Why are ROMs called nonvolatile memory? |
| A. | They lose memory when power is removed. |
| B. | They do not lose memory when power is removed. |
| Answer» C. | |
| 852. |
A CD-R disk is created by applying heat to special chemicals on the disk and these chemicals reflect less light than the areas that are not burned, thus creating the same effect as a pit does on a regular CD. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 853. |
How many 1K 4 RAM chips would be required to build a 1K 8 memory system? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» B. 4 | |
| 854. |
Which of the following memories uses a MOS capacitor as its memory cell? |
| A. | SRAM |
| B. | DRAM |
| C. | ROM |
| D. | FIFO |
| Answer» C. ROM | |
| 855. |
Which of the following faults will the checkerboard pattern test for in RAM? |
| A. | Short between adjacent cells |
| B. | Ability to store both 0s and 1s |
| C. | Dynamically introduced errors between cells |
| D. | All of the above |
| Answer» E. | |
| 856. |
Select the statement that best describes the fusible-link PROM. |
| A. | user-programmable, one-time programmable |
| B. | manufacturer-programmable, one-time programmable |
| C. | user-programmable, reprogrammable |
| D. | manufacturer-programmable, reprogrammable |
| Answer» B. manufacturer-programmable, one-time programmable | |
| 857. |
How can UV erasable PROMs be recognized? |
| A. | There is a small window on the chip. |
| B. | They will have a small violet dot next to the #1 pin. |
| C. | Their part number always starts with a "U", such as in U12. |
| D. | They are not readily identifiable, since they must always be kept under a small cover. |
| Answer» B. They will have a small violet dot next to the #1 pin. | |
| 858. |
What part of a Flash memory architecture manages all chip functions? |
| A. | I/O pins |
| B. | floating-gate MOSFET |
| C. | command code |
| D. | program verify code |
| Answer» C. command code | |
| 859. |
An 8-bit address code can select ________. |
| A. | 8 locations in memory |
| B. | 256 locations in memory |
| C. | 65,536 locations in memory |
| D. | 131,072 locations in memory |
| Answer» C. 65,536 locations in memory | |
| 860. |
Eight bits of digital data are normally referred to as a: |
| A. | group. |
| B. | byte. |
| C. | word. |
| D. | cell. |
| Answer» C. word. | |
| 861. |
The smallest unit of binary data is the ________. |
| A. | bit |
| B. | nibble |
| C. | byte |
| D. | word |
| Answer» B. nibble | |
| 862. |
What is the preset condition for a ring shift counter? |
| A. | all FFs set to 1 |
| B. | all FFs cleared to 0 |
| C. | a single 0, the rest 1 |
| D. | a single 1, the rest 0 |
| Answer» E. | |
| 863. |
Which is not characteristic of a shift register? |
| A. | Serial in/parallel in |
| B. | Serial in/parallel out |
| C. | Parallel in/serial out |
| D. | Parallel in/parallel out |
| Answer» B. Serial in/parallel out | |
| 864. |
To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________. |
| A. | divide-by-4 clock pulse |
| B. | sequence generator |
| C. | strobe line |
| D. | multiplexer |
| Answer» D. multiplexer | |
| 865. |
What is the difference between a shift-right register and a shift-left register? |
| A. | There is no difference. |
| B. | the direction of the shift |
| Answer» C. | |
| 866. |
What is a transceiver circuit? |
| A. | a buffer that transfers data from input to output |
| B. | a buffer that transfers data from output to input |
| C. | a buffer that can operate in both directions |
| Answer» D. | |
| 867. |
A 74HC195 4-bit parallel access shift register can be used for ________. |
| A. | serial in/serial out operation |
| B. | serial in/parallel out operation |
| C. | parallel in/serial out operation |
| D. | all of the above |
| Answer» E. | |
| 868. |
By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register. |
| A. | parallel-in, serial, parallel |
| B. | serial-in, parallel, serial |
| C. | series-parallel-in, series, parallel |
| D. | bidirectional in, parallel, series |
| Answer» B. serial-in, parallel, serial | |
| 869. |
What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time? |
| A. | parallel-in, parallel-out |
| B. | parallel-in, serial-out |
| C. | serial-in, parallel-out |
| D. | serial-in, serial-out |
| Answer» D. serial-in, serial-out | |
| 870. |
Which type of device may be used to interface a parallel data format with external equipment's serial format? |
| A. | key matrix |
| B. | UART |
| C. | memory chip |
| D. | series in, parallel out |
| Answer» C. memory chip | |
| 871. |
What is the function of a buffer circuit? |
| A. | to provide an output that is inverted from that on the input |
| B. | to provide an output that is equal to its input |
| C. | to clean up the input |
| D. | to clean up the output |
| Answer» C. to clean up the input | |
| 872. |
When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________. |
| A. | 40 kHz |
| B. | 50 kHz |
| C. | 400 kHz |
| D. | 500 kHz |
| Answer» D. 500 kHz | |
| 873. |
Ring shift and Johnson counters are: |
| A. | synchronous counters |
| B. | aynchronous counters |
| C. | true binary counters |
| D. | synchronous and true binary counters |
| Answer» B. aynchronous counters | |
| 874. |
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. |
| A. | 1110 |
| B. | 0111 |
| C. | 1000 |
| D. | 1001 |
| Answer» E. | |
| 875. |
In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. |
| A. | 1110 |
| B. | 0001 |
| C. | 1100 |
| D. | 1000 |
| Answer» C. 1100 | |
| 876. |
The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. |
| A. | 10111000 |
| B. | 10110111 |
| C. | 11110000 |
| D. | 11111100 |
| Answer» E. | |
| 877. |
Determine the two's-complement of each binary number.00110 00011 11101 |
| A. | 11001 11100 00010 |
| B. | 00111 00010 00010 |
| C. | 00110 00011 11101 |
| D. | 11010 11101 00011 |
| Answer» E. | |
| 878. |
________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates. |
| A. | Simplified AND gates |
| B. | Fuses |
| C. | Buffers |
| D. | Latches |
| Answer» D. Latches | |
| 879. |
Which is not a part of a GAL16V8's OLMC? |
| A. | TSMUX |
| B. | OMUX |
| C. | FMUX |
| D. | PSMUX |
| Answer» E. | |
| 880. |
What is PROM? |
| A. | SPLD |
| B. | QPLD |
| C. | HPLD |
| D. | PLD |
| Answer» E. | |
| 881. |
A slice consists of ________. |
| A. | only two logic cells |
| B. | between 2 and 8 logic cells |
| C. | up to 16 logic cells |
| D. | a single CLB |
| Answer» B. between 2 and 8 logic cells | |
| 882. |
Product terms are the outputs of which type of gate within a PLD array? |
| A. | OR |
| B. | XOR |
| C. | AND |
| D. | flip-flop |
| Answer» D. flip-flop | |
| 883. |
The 8051 can handle ________ interrupt sources. |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» D. 6 | |
| 884. |
Which is not a type of PLD? |
| A. | SPLD |
| B. | HPLD |
| C. | CPLD |
| D. | FPGA |
| Answer» C. CPLD | |
| 885. |
Which type of PLD could be used to program basic logic functions? |
| A. | PLA |
| B. | PAL |
| C. | CPLD |
| D. | all the above |
| Answer» E. | |
| 886. |
An SPLD listed as 16H8 would have ________. |
| A. | active-HIGH outputs |
| B. | active-LOW outputs |
| C. | variable-level outputs |
| D. | latches at the outputs |
| Answer» B. active-LOW outputs | |
| 887. |
The special function registers are maintained in the next 128 locations after the general-purpose data storage and stack. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 888. |
This statement will set the address of the bit to 1 (8051 Micro-controller): SETB 01H |
| A. | True |
| B. | False |
| Answer» C. | |
| 889. |
Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder? |
| A. | to decrease the cost |
| B. | to make it smaller |
| C. | to slow down the circuit |
| D. | to speed up the circuit |
| Answer» E. | |
| 890. |
What logic function is the sum output of a half-adder? |
| A. | AND |
| B. | exclusive-OR |
| C. | exclusive-NOR |
| D. | NAND |
| Answer» C. exclusive-NOR | |
| 891. |
The binary adder circuit is designed to add ________ binary numbers at the same time. |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» B. 4 | |
| 892. |
Subtract the following hexadecimal numbers. 47 &nbsp 34 &nbsp FA 25 &nbsp 1C &nbsp 2F |
| A. | 22 18 CB |
| B. | 22 17 CB |
| C. | 22 19 CB |
| D. | 22 18 CC |
| Answer» B. 22 17 CB | |
| 893. |
What is the correct output of the adder in the given figure, with the outputs in the order: |
| A. | 10111 |
| B. | 11101 |
| C. | 01101 |
| D. | 10011 |
| Answer» B. 11101 | |
| 894. |
Solve this binary problem: |
| A. | 11001001 |
| B. | 10010000 |
| C. | 01101110 |
| D. | 01110110 |
| Answer» C. 01101110 | |
| 895. |
The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to: |
| A. | ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros |
| B. | add 0110 to both code groups to validate the carry from the lowest order code group |
| C. | disregard the carry and add 0110 to the lowest order code group |
| D. | add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros |
| Answer» E. | |
| 896. |
Convert each of the decimal numbers to two's-complement form and perform the addition in binary. +13&nbsp 10 add 7&nbspadd +15 |
| A. | 0001 0100 0000 0101 |
| B. | 0000 0110 0001 1001 |
| C. | 0000 0110 0000 0101 |
| D. | 1111 0110 1111 0101 |
| Answer» D. 1111 0110 1111 0101 | |
| 897. |
Add the following binary numbers. 0010 0110 &nbsp 0011 1011 &nbsp 0011 1100 +0101 0101 &nbsp +0001 1110 &nbsp +0001 1111 |
| A. | 0111 1011 0100 0001 0101 1011 |
| B. | 0111 1011 0101 1001 0101 1011 |
| C. | 0111 0111 0101 1001 0101 1011 |
| D. | 0111 0111 0100 0001 0101 1011 |
| Answer» C. 0111 0111 0101 1001 0101 1011 | |
| 898. |
The summing outputs of a half- or full-adder are designated by which Greek symbol? |
| A. | omega |
| B. | theta |
| C. | lambda |
| D. | sigma |
| Answer» E. | |
| 899. |
The carry propagation delay in full-adder circuits: |
| A. | is normally not a consideration because the delays are usually in the nanosecond range. |
| B. | decreases in a direct ratio to the total number of FA stages. |
| C. | is cumulative for each stage and limits the speed at which arithmetic operations are performed. |
| D. | increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations. |
| Answer» D. increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations. | |
| 900. |
Could the sum output of a full-adder be used as a two-bit parity generator? |
| A. | Yes |
| B. | No |
| Answer» B. No | |