MCQOPTIONS
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MCQOPTIONS
This section includes 2291 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 801. |
The ideal memory ________. |
| A. | has high storage capacity |
| B. | is nonvolatile |
| C. | has in-system read and write capacity |
| D. | has all of the above characteristics |
| Answer» E. | |
| 802. |
What is the bit storage capacity of a ROM with a 1024 8 organization? |
| A. | 1024 |
| B. | 2048 |
| C. | 4096 |
| D. | 8192 |
| Answer» E. | |
| 803. |
The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________. |
| A. | 4096 |
| B. | 8129 |
| C. | 16358 |
| D. | 32768 |
| Answer» D. 32768 | |
| 804. |
How many 8 k 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits? |
| A. | Eight |
| B. | Four |
| C. | Two |
| D. | One |
| Answer» B. Four | |
| 805. |
On a CD-ROM, ________ are recessed areas representing a 0. |
| A. | mounds |
| B. | lands |
| C. | holes |
| D. | pits |
| Answer» E. | |
| 806. |
Which of the following is not a flash memory mode or operation? |
| A. | Burst |
| B. | Read |
| C. | Erase |
| D. | Programming |
| Answer» B. Read | |
| 807. |
Why is a refresh cycle necessary for a dynamic RAM? |
| A. | to clear the flip-flops |
| B. | to set the flip-flops |
| C. | The refresh cycle discharges the capacitor cells. |
| D. | The refresh cycle keeps the charge on the capacitor cells. |
| Answer» E. | |
| 808. |
Which is not a magnetic storage device? |
| A. | Magnetic disk |
| B. | Magnetic tape |
| C. | Magneto-optical disk |
| D. | Optical disk |
| Answer» E. | |
| 809. |
The time from the beginning of a read cycle to the end of tACS or tAA is referred to as: |
| A. | access time |
| B. | data hold |
| C. | read cycle time |
| D. | write enable time |
| Answer» B. data hold | |
| 810. |
Which of the following memories is volatile? |
| A. | ROM |
| B. | EROM |
| C. | RAM |
| D. | Flash |
| Answer» D. Flash | |
| 811. |
The mask ROM is ________. |
| A. | permanently programmed during the manufacturing process |
| B. | volatile |
| C. | easy to reprogram |
| D. | extremely expensive |
| Answer» B. volatile | |
| 812. |
The periodic recharging of DRAM memory cells is called ________. |
| A. | multiplexing |
| B. | bootstrapping |
| C. | refreshing |
| D. | flashing |
| Answer» D. flashing | |
| 813. |
What are the typical values of tOE? |
| A. | 10 to 20 ns for bipolar |
| B. | 25 to 100 ns for NMOS |
| C. | 12 to 50 ns for CMOS |
| D. | All of the above |
| Answer» E. | |
| 814. |
How many address lines would be required for a 2K 4 memory chip? |
| A. | 8 |
| B. | 10 |
| C. | 11 |
| D. | 12 |
| Answer» D. 12 | |
| 815. |
Which of the following is normally used to initialize a computer system's hardware? |
| A. | Bootstrap memory |
| B. | Volatile memory |
| C. | External mass memory |
| D. | Static memory |
| Answer» B. Volatile memory | |
| 816. |
What is the difference between static RAM and dynamic RAM? |
| A. | Static RAM must be refreshed, dynamic RAM does not. |
| B. | There is no difference. |
| C. | Dynamic RAM must be refreshed, static RAM does not. |
| Answer» D. | |
| 817. |
Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________. |
| A. | buffered |
| B. | decoded |
| C. | addressed |
| D. | stored |
| Answer» B. decoded | |
| 818. |
When a RAM module passes the checkerboard test it is: |
| A. | able to read and write only 1s. |
| B. | faulty. |
| C. | probably good. |
| D. | able to read and write only 0s. |
| Answer» D. able to read and write only 0s. | |
| 819. |
Which type of ROM has to be custom built by the factory? |
| A. | ROM |
| B. | mask ROM |
| C. | EPROM |
| D. | EEPROM |
| Answer» C. EPROM | |
| 820. |
What is the computer main memory? |
| A. | Hard drive and RAM |
| B. | CD-ROM and hard drive |
| C. | RAM and ROM |
| D. | CMOS and hard drive |
| Answer» D. CMOS and hard drive | |
| 821. |
A major disadvantage of the mask ROM is that it: |
| A. | is time consuming to change the stored data when system requirements change |
| B. | is very expensive to change the stored data when system requirements change |
| C. | cannot be reprogrammed if stored data needs to be changed |
| D. | has an extremely short life expectancy and requires frequent replacement |
| Answer» D. has an extremely short life expectancy and requires frequent replacement | |
| 822. |
Which type of ROM can be erased by an electrical signal? |
| A. | ROM |
| B. | mask ROM |
| C. | EPROM |
| D. | EEPROM |
| Answer» E. | |
| 823. |
Suppose that a certain semiconductor memory chip has a capacity of 8K 8. How many bytes could be stored in this device? |
| A. | 8,000 |
| B. | 64,000 |
| C. | 65,536 |
| D. | 8,192 |
| Answer» E. | |
| 824. |
Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive. |
| A. | cylinder |
| B. | read/write |
| C. | recordable |
| D. | cluster |
| Answer» C. recordable | |
| 825. |
CCD stands for ________. |
| A. | capacitor charging device |
| B. | capacitor-capacitor drain |
| C. | charged-capacitor device |
| D. | charge-coupled device |
| Answer» E. | |
| 826. |
What is the major difference between SRAM and DRAM? |
| A. | DRAMs must be periodically refreshed. |
| B. | SRAMs can hold data via a static charge, even with power off. |
| C. | The only difference is the terminal from which the data is removed from the FET Drain or Source. |
| D. | Dynamic RAMs are always active; static RAMs must reset between data read/write cycles. |
| Answer» B. SRAMs can hold data via a static charge, even with power off. | |
| 827. |
What is a major disadvantage of RAM? |
| A. | Its access speed is too slow. |
| B. | Its matrix size is too big. |
| C. | It is volatile. |
| D. | High power consumption |
| Answer» D. High power consumption | |
| 828. |
What two functions does a DRAM controller perform? |
| A. | address multiplexing and data selection |
| B. | address multiplexing and the refresh operation |
| C. | data selection and the refresh operation |
| D. | data selection and CPU accessing |
| Answer» C. data selection and the refresh operation | |
| 829. |
Which of the following best describes volatile memory? |
| A. | memory that retains stored information when electrical power is removed |
| B. | memory that loses stored information when electrical power is removed |
| C. | magnetic memory |
| D. | nonmagnetic |
| Answer» C. magnetic memory | |
| 830. |
Dynamic memory cells store a data bit in a ________. |
| A. | diode |
| B. | resistor |
| C. | capacitor |
| D. | flip-flop |
| Answer» D. flip-flop | |
| 831. |
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________. |
| A. | 4 s |
| B. | 40 s |
| C. | 400 s |
| D. | 40 ms |
| Answer» C. 400 s | |
| 832. |
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit? |
| A. | ring shift |
| B. | clock |
| C. | Johnson |
| D. | binary |
| Answer» B. clock | |
| 833. |
The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses? |
| A. | 10011100 |
| B. | 11000000 |
| C. | 00001100 |
| D. | 11110000 |
| Answer» C. 00001100 | |
| 834. |
If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse? |
| A. | 11101011 |
| B. | 00010111 |
| C. | 11110000 |
| D. | 00000000 |
| Answer» B. 00010111 | |
| 835. |
Which of the following best describes static memory devices? |
| A. | memory devices that are magnetic in nature and do not require constant refreshing |
| B. | memory devices that are magnetic in nature and require constant refreshing |
| C. | semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed |
| D. | semiconductor memory devices in which stored data is retained as long as power is applied |
| Answer» E. | |
| 836. |
Which is not a removable drive? |
| A. | Zip |
| B. | Jaz |
| C. | Hard |
| D. | SuperDisk |
| Answer» D. SuperDisk | |
| 837. |
Which of the following best describes EPROMs? |
| A. | EPROMs can be programmed only once. |
| B. | EPROMs can be erased by UV. |
| C. | EPROMs can be erased by shorting all inputs to the ground. |
| D. | All of the above. |
| Answer» C. EPROMs can be erased by shorting all inputs to the ground. | |
| 838. |
How many storage locations are available when a memory device has 12 address lines? |
| A. | 144 |
| B. | 512 |
| C. | 2048 |
| D. | 4096 |
| Answer» E. | |
| 839. |
FIFO is formed by an arrangement of ________. |
| A. | diodes |
| B. | transistors |
| C. | MOS cells |
| D. | shift registers |
| Answer» E. | |
| 840. |
Why do most dynamic RAMs use a multiplexed address bus? |
| A. | It is the only way to do it. |
| B. | to make it faster |
| C. | to keep the number of pins on the chip to a minimum |
| Answer» D. | |
| 841. |
Which is/are the basic refresh mode(s) for dynamic RAM? |
| A. | Burst refresh |
| B. | Distributed refresh |
| C. | Open refresh |
| D. | Burst refresh and distributed refresh |
| Answer» E. | |
| 842. |
For the given circuit, what memory location is being addressed? |
| A. | 10111 |
| B. | 249 |
| C. | 5 |
| D. | 157 |
| Answer» C. 5 | |
| 843. |
One of the most important specifications on magnetic media is the ________. |
| A. | rotation speed |
| B. | tracks per inch |
| C. | data transfer rate |
| D. | polarity reversal rate |
| Answer» D. polarity reversal rate | |
| 844. |
A 64-bit word consists of ________. |
| A. | 4 bytes |
| B. | 8 bytes |
| C. | 10 bytes |
| D. | 12 bytes |
| Answer» C. 10 bytes | |
| 845. |
The reason the data outputs of most ROM ICs are tristate outputs is to: |
| A. | allow for three separate data input lines. |
| B. | allow the bidirectional flow of data between the bus lines and the ROM registers. |
| C. | permit the connection of many ROM chips to a common data bus. |
| D. | isolate the registers from the data bus during read operations. |
| Answer» D. isolate the registers from the data bus during read operations. | |
| 846. |
How many 2K 8 ROM chips would be required to build a 16K 8 memory system? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» D. 16 | |
| 847. |
For the given circuit, which of the following is correct? |
| A. | The number 5 is being written to the memory at address location 203. |
| B. | The chip has not been enabled, since the EN terminal is 0; therefore, nothing will be written to the chip and the output is tri-stated. |
| C. | Decimal 10 is being written into memory location 211. |
| D. | The read/write line is LOW; therefore, decimal 5 is being stored at memory location 211. |
| Answer» D. The read/write line is LOW; therefore, decimal 5 is being stored at memory location 211. | |
| 848. |
What is the significance of the inverted triangles on the outputs of the device in the given figure? |
| A. | They represent inverters and mean that the outputs are active-LOW. |
| B. | They represent buffers and mean that the outputs can drive 40 TTL loads, instead of the normal 10. |
| C. | It means that the outputs will be active only if a change has occurred at that memory location since the last read/write cycle. |
| D. | The outputs are tristated. |
| Answer» E. | |
| 849. |
What is the maximum time required before a dynamic RAM must be refreshed? |
| A. | 2 ms |
| B. | 4 ms |
| C. | 8 ms |
| D. | 10 ms |
| Answer» B. 4 ms | |
| 850. |
Which of the following best describes random-access memory (RAM)? |
| A. | a type of memory in which access time depends on memory location |
| B. | a type of memory that can be written to only once but can be read from an infinite number of times |
| C. | a type of memory in which access time is the same for each memory location |
| D. | mass memory |
| Answer» D. mass memory | |