MCQOPTIONS
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MCQOPTIONS
This section includes 646 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 251. |
The circuit produces a HIGH output whenever the two inputs are equal. |
| A. | exclusive-and |
| B. | exclusive- nand |
| C. | exclusive- nor |
| D. | exclusive- or |
| Answer» D. exclusive- or | |
| 252. |
The series of IC's are pin, function, and voltage-level compatible with the 74 series IC's. |
| A. | als |
| B. | cmos |
| C. | hct |
| D. | 2n |
| Answer» D. 2n | |
| 253. |
After each circuit in a subsection of a VHDL program has been , they can be combined and the subsection can be tested. |
| A. | designed |
| B. | tested |
| C. | engineered |
| D. | produced |
| Answer» C. engineered | |
| 254. |
The final output of a POS circuit is generated by . |
| A. | an and |
| B. | an or |
| C. | a nor |
| D. | a nand |
| Answer» B. an or | |
| 255. |
When Karnaugh mapping, we must be sure to use the number of loops. |
| A. | maximum |
| B. | minimum |
| C. | median |
| D. | karnaugh |
| Answer» C. median | |
| 256. |
Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected . |
| A. | to the outputs from the least significant 4- bit comparator |
| B. | to the cascading inputs of the least significant 4- bit comparator |
| C. | a = b to a logic high, a < b and a > b to a logic low |
| D. | ground |
| Answer» B. to the cascading inputs of the least significant 4- bit comparator | |
| 257. |
An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if . |
| A. | the number is odd |
| B. | the number of 1s in the number is odd |
| C. | the number is even |
| D. | the number of 1s in the number is even |
| Answer» E. | |
| 258. |
A Karnaugh map will . |
| A. | eliminate the need for tedious boolean simplifications |
| B. | allow any circuit to be implemented with just and and or gates |
| C. | produce the simplest sum-of- products expression |
| D. | give an overall picture of how the signals flow through the logic circuit |
| Answer» B. allow any circuit to be implemented with just and and or gates | |
| 259. |
The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must . |
| A. | be positive |
| B. | be negative |
| C. | have the same sign |
| D. | have opposite signs |
| Answer» D. have opposite signs | |
| 260. |
To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is               . |
| A. | complemented only if it is positive |
| B. | complemente d only if it is negative |
| C. | always complemente d |
| D. | never compleme nted |
| Answer» E. | |
| 261. |
In an odd-parity system, the data that will produce a parity bit = 1 is               . |
| A. | data = 1010011 |
| B. | data = 1111000 |
| C. | data = 1100000 |
| D. | all of the above |
| Answer» E. | |
| 262. |
When an open occurs on the input of a CMOS gate, the output will . |
| A. | go low, because there is no current in an open circuit |
| B. | react as if the open input were a high |
| C. | go high, since full voltage appears across an open |
| D. | be unpredicta ble; it may go high or low |
| Answer» E. | |
| 263. |
One reason for using the sum-of-products form is that it can be implemented using all gates without much difficulty. |
| A. | nor |
| B. | nand |
| C. | and |
| D. | door |
| Answer» C. and | |
| 264. |
The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to . |
| A. | turn off the display for any nonsignificant digit |
| B. | turn off the display for any zero |
| C. | turn off the display for leading or trailing zeros |
| D. | test the display to assure all segments are operationa l |
| Answer» B. turn off the display for any zero | |
| 265. |
Parity generators and checkers use gates. |
| A. | exclusive-and |
| B. | exclusive- or/nor |
| C. | exclusive-or |
| D. | exclusive- nand |
| Answer» C. exclusive-or | |
| 266. |
The AND-OR-INVERT gates are designed to simplify implementation of . |
| A. | pos logic |
| B. | demorgan\s theorem |
| C. | nand logic |
| D. | sop logic |
| Answer» C. nand logic | |
| 267. |
The output of a gate has an internal short; a current tracer will . |
| A. | identify the defective gate |
| B. | show whether the gate is shorted to v cc or ground |
| C. | probably not be able to locate the problem |
| D. | be able to identify the defective load node |
| Answer» B. show whether the gate is shorted to v cc or ground | |
| 268. |
A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) . |
| A. | xor gate |
| B. | xnor gate |
| C. | nand gate |
| D. | nor gate |
| Answer» C. nand gate | |
| 269. |
Except for , STD_LOGIC may have the following values. |
| A. | \z\ |
| B. | \u\ |
| C. | \?\ |
| D. | \l\ |
| Answer» D. \l\ | |
| 270. |
VHDL is very strict in the way it allows us to assign and compare                such as signals, variables, constants, and literals. |
| A. | objects |
| B. | logic_vect ors |
| C. | designs |
| D. | arrays |
| Answer» B. logic_vect ors | |
| 271. |
Parity generation and checking is used to detect . |
| A. | which of two numbers is greater |
| B. | errors in binary data transmission |
| C. | errors in arithmetic in computers |
| D. | when a binary counter counts incorrectly |
| Answer» C. errors in arithmetic in computers | |
| 272. |
The largest truth table that can be implemented directly with an 8-line- to-1-line MUX has . |
| A. | 3 rows |
| B. | 4 rows |
| C. | 8 rows |
| D. | 16 rows |
| Answer» D. 16 rows | |
| 273. |
When an open occurs on the input of a TTL device, the output will . |
| A. | go low, because there is no current in an open circuit |
| B. | react as if the open input were a high |
| C. | go high, since full voltage appears across an open |
| D. | still be good, if only the good inputs are used |
| Answer» C. go high, since full voltage appears across an open | |
| 274. |
The prefix on IC's indicates a broader operating temperature range, and the devices are generally used by the military. |
| A. | 54 |
| B. | 2n |
| C. | 74 |
| D. | ttl |
| Answer» B. 2n | |
| 275. |
A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a . |
| A. | priority encoder |
| B. | decoder |
| C. | multiplexer |
| D. | demultiple xer |
| Answer» B. decoder | |
| 276. |
A half-adder does not have . |
| A. | carry in |
| B. | carry out |
| C. | two inputs |
| D. | all of the above |
| Answer» B. carry out | |
| 277. |
How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» C. 5 | |
| 278. |
What is the indication of a short to ground in the output of a driving gate? |
| A. | only the output of the defective gate is affected. |
| B. | there is a signal loss to all load gates. |
| C. | the node may be stuck in either the high or the low state. |
| D. | the affected node will be stuck in the high state. |
| Answer» C. the node may be stuck in either the high or the low state. | |
| 279. |
Which of the following combinations of logic gates can decode binary 1101? |
| A. | one 4-input and gate |
| B. | one 4-input and gate, one or gate |
| C. | one 4-input nand gate, one inverter |
| D. | one 4- input and gate, one inverter |
| Answer» E. | |
| 280. |
When adding an even parity bit to the code 110010, the result is . |
| A. | 1110010 |
| B. | 110010 |
| C. | 1111001 |
| D. | 1101 |
| Answer» B. 110010 | |
| 281. |
A certain BCD-to-decimal decoder has active-HIGH inputs and active- LOW outputs. Which output goes LOW when the inputs are 1001? |
| A. | 0 |
| B. | 3 |
| C. | 9 |
| D. | none. all outputs are high. |
| Answer» D. none. all outputs are high. | |
| 282. |
A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A = 1 and B = 1? |
| A. | = 0, cout = 0 |
| B. | = 0, cout = 1 |
| C. | = 1, cout = 0 |
| D. | = 1, cout = 1 |
| Answer» C. = 1, cout = 0 | |
| 283. |
How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 284. |
A decoder can be used as a demultiplexer by . |
| A. | tying all enable pins low |
| B. | tying all data-select lines low |
| C. | tying all data- select lines high |
| D. | using the input lines for data selection and an enable line for data input |
| Answer» E. | |
| 285. |
The carry propagation can be expressed as . |
| A. | cp = ab |
| B. | cp = a + b |
| C. | |
| Answer» C. | |
| 286. |
In HDL, LITERALS is/are: |
| A. | digital systems. |
| B. | scalars. |
| C. | binary coded decimals. |
| D. | a numbering system. |
| Answer» C. binary coded decimals. | |
| 287. |
What is the indication of a short on the input of a load gate? |
| A. | only the output of the defective gate is affected. |
| B. | there is a signal loss to all gates on the node. |
| C. | the affected node will be stuck in the low state. |
| D. | there is a signal loss to all gates on the node, and the affected node will be stuck in the low state. |
| Answer» E. | |
| 288. |
What will a design engineer do after he/she is satisfied that the design will work? |
| A. | put it in a flow chart |
| B. | program a chip and test it |
| C. | give the design to a technician to verify the design |
| D. | perform a vector test |
| Answer» C. give the design to a technician to verify the design | |
| 289. |
Looping on a K-map always results in the elimination of: |
| A. | variables within the loop that appear only in their complemented form. |
| B. | variables that remain unchanged within the loop. |
| C. | variables within the loop that appear in both complemente d and uncompleme nted form. |
| D. | variables within the loop that appear only in their uncomple mented form. |
| Answer» D. variables within the loop that appear only in their uncomple mented form. | |
| 290. |
Each "1" entry in a K-map square represents: |
| A. | a high for each input truth table condition that produces a high output. |
| B. | a high output on the truth table for all low input combination s. |
| C. | a low output for all possible high input conditions. |
| D. | a don\t care condition for all possible input truth table combinati ons. |
| Answer» B. a high output on the truth table for all low input combination s. | |
| 291. |
A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? |
| A. | the output of the gate appears to be open. |
| B. | the dim indication on the logic probe indicates that the supply voltage is probably low. |
| C. | the dim indication is a result of a bad ground connection on the logic probe. |
| D. | the gate may be a tristate device. |
| Answer» B. the dim indication on the logic probe indicates that the supply voltage is probably low. | |
| 292. |
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? |
| A. | a > b = 1, a < b = 0, a < b = 1 |
| B. | a > b = 0, a < b = 1, a = b = 0 |
| C. | a > b = 1, a < b = 0, a = b = 0 |
| D. | a > b = 0, a < b = 1, a = b = 1 |
| Answer» D. a > b = 0, a < b = 1, a = b = 1 | |
| 293. |
An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem? |
| A. | current tracer |
| B. | logic probe |
| C. | oscilloscope |
| D. | logic analyzer |
| Answer» B. logic probe | |
| 294. |
Which of the following is an important feature of the sum-of-products form of expressions? |
| A. | all logic circuits are reduced to nothing more than simple and and or operations. |
| B. | the delay times are greatly reduced over other forms. |
| C. | no signal must pass through more than two gates, not including inverters. |
| D. | the maximum number of gates that any signal must pass through is reduced by a factor of two. |
| Answer» B. the delay times are greatly reduced over other forms. | |
| 295. |
Which of the following expressions is in the product-of-sums form? |
| A. | (a + b )(c + d ) |
| B. | (ab )(cd ) |
| C. | ab (cd ) |
| D. | ab + cd |
| Answer» B. (ab )(cd ) | |
| 296. |
For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs? |
| A. | all are high. |
| B. | all are low. |
| C. | all but are low. |
| D. | all but are high. |
| Answer» B. all are low. | |
| 297. |
In VHDL, macrofunctions is/are: |
| A. | digital circuits. |
| B. | analog circuits. |
| C. | a set of bit vectors. |
| D. | preprogra mmed ttl devices. |
| Answer» E. | |
| 298. |
The device shown here is most likely a . |
| A. | comparator |
| B. | multiplexer |
| C. | demultiplexe r |
| D. | parity generator |
| Answer» D. parity generator | |
| 299. |
Which gate is best used as a basic comparator? |
| A. | nor |
| B. | or |
| C. | exclusive-or |
| D. | and |
| Answer» D. and | |
| 300. |
As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem. |
| A. | a defective ic chip that is drawing excessive current from the power supply |
| B. | a solar bridge between the inputs on the first ic chip on the board |
| C. | an open input on the first ic chip on the board |
| D. | a defective output ic chip that has an internal open to v cc |
| Answer» D. a defective output ic chip that has an internal open to v cc | |