646 + Mcqs in Digital Electronics And Logic Design Page 4 McqOptions

151.	A decade counter is .
A.	mod-3 counter
B.	mod-5 counter
C.	mod-8 counter
D.	mod-10 counter
Answer» E.

Discussion

152.	The input overrides the input
A.	asynchronous , synchronous
B.	synchronous, asynchronou s
C.	preset input (pre), clear input (clr)
D.	clear input (clr), preset input (pre)
Answer» B. synchronous, asynchronou s

Discussion

153.	The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.
A.	set-up time
B.	hold time
C.	pulse interval time
D.	pulse stability time (pst)
Answer» C. pulse interval time

Discussion

154.	74HC163 has two enable input pins which are and
A.	enp, ent
B.	eni, enc
C.	enp, enc
D.	ent, eni
Answer» B. eni, enc

Discussion

155.	In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
A.	true
B.	false
Answer» B. false

Discussion

156.	The divide-by-60 counter in digital clock is implemented by using two cascading counters:
A.	mod-6, mod-10
B.	mod-50, mod-10
C.	mod-10, mod-50
D.	mod-50, mod-6
Answer» B. mod-50, mod-10

Discussion

157.	In a sequential circuit the next state is determined by and
A.	state variable, current state
B.	current state, flip- flop output
C.	current state and external input
D.	input and clock signal applied
Answer» E.

Discussion

158.	A 8-bit serial in / parallel out shift register contains the value â€œ8â€, Â Â Â Â Â Â Â Â Â clock signal(s) will be required to shift the value completely out of the register.
A.	1
B.	2
C.	4
D.	8
Answer» E.

Discussion

159.	The number of flip-flops required in a decade counter is
A.	3
B.	4
C.	8
D.	10
Answer» C. 8

Discussion

160.	Register is a
A.	set of capacitor used to register input instructions in a digital computer
B.	set to paper tapes and cards put in a file
C.	temporary storage unit within the cpu having dedicated or general purpose use
D.	part of the main memory
Answer» D. part of the main memory

Discussion

161.	If in a shift resistor Q0 is fed back to input the resulting counter is
A.	twisted ring with n : 1 scale
B.	ring counter with n : 1 scale
C.	twisted ring with 2n : 1 scale
D.	ring counter with 2 n : 1 scale
Answer» D. ring counter with 2 n : 1 scale

Discussion

162.	If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
A.	nt sec
B.	(n-1)t sec
C.	n/t sec
D.	(2n+1)t sec
Answer» C. n/t sec

Discussion

163.	If the input J is connected through K input of J-K, then flip-flop will behave as a
A.	d type flip-flop
B.	t type flip- flop
C.	s-r flip-flop
D.	master slave jk flip-flop
Answer» B. t type flip- flop

Discussion

164.	Which of the following flip-flop is free from race-around problem ?
A.	q flip-flop
B.	t flip-flop
C.	sr flip-flop
D.	master- slave jk flip-flop
Answer» E.

Discussion

165.	Which of the following unit will choose to transform decimal number to binary code ?
A.	encoder
B.	decoder
C.	multiplexer
D.	counter
Answer» B. decoder

Discussion

166.	The flip-flops which operate in synchronism with external clock pulses are known as
A.	synchronous flip-flop
B.	asynchronou s flip-flop
C.	either of the above
D.	none of these
Answer» B. asynchronou s flip-flop

Discussion

167.	The main difference between JK and RS flip-flop is that
A.	jk flip flop needs a clock pulse
B.	there is a feedback in jk lip-lop
C.	jk flip-flop accepts both inputs as 1
D.	jk flip-flop is acronym of junction cathode multivibra tor
Answer» D. jk flip-flop is acronym of junction cathode multivibra tor

Discussion

168.	41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the
A.	clock input of all flip-flops
B.	clock input of one flip- flops
C.	j and k inputs of all flip-flops
D.	j and k inputs of one flip- flop
Answer» D. j and k inputs of one flip- flop

Discussion

169.	How many flip-flop are needed to divide the input frequency by 64 ?
A.	2
B.	5
C.	6
D.	8
Answer» D. 8

Discussion

170.	The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is
A.	10
B.	12
C.	16
D.	32
Answer» D. 32

Discussion

171.	It is difficult to design asynhronous sequential circuit because
A.	external clock is to be provided
B.	it is more complex
C.	both (a) and (b)
D.	generally they involve stability problem
Answer» E.

Discussion

172.	The master slave JK lip-flop is effectively a combination of
A.	a sr flip-flop and a t flip- flop
B.	an sr flip- lfop and a d flip-flop
C.	a t flip-flop and a d flip- flop
D.	two d flip- flops
Answer» B. an sr flip- lfop and a d flip-flop

Discussion

173.	A stable multivibrator is used as
A.	comparator circuit
B.	demultiplexe r
C.	frequency to voltage converter
D.	voltage to frequency converter
Answer» B. demultiplexe r

Discussion

174.	The functional difference between S-R flip-flop and J-K flip-flop is that J- K flip-flop
A.	is faster than s- r flip-flop
B.	has a feed- back path
C.	accepts both inputs 1
D.	both (a) and (b)
Answer» D. both (a) and (b)

Discussion

175.	A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be
A.	1 mhz
B.	2 mhz
C.	6 mhz
D.	8 mhz
Answer» E.

Discussion

176.	When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is
A.	jk flip-flop
B.	d flip-flop
C.	sr flip-flop
D.	master slave jk flip-flop
Answer» C. sr flip-flop

Discussion

177.	In a positive edge triggered JK flip-flop, a low J and low K produces
A.	no change
B.	low state
C.	high state
D.	none of thes
Answer» B. low state

Discussion

178.	How many bits are required to encode all twenty six letters, ten symbols, and ten numerals ?
A.	5
B.	6
C.	10
D.	48
Answer» C. 10

Discussion

179.	The astable multivibrator has
A.	two quasi stable states
B.	two stable states
C.	one stable and one quasi-stable state
D.	none of these
Answer» B. two stable states

Discussion

180.	To build a mod-19 counter the number of flip-flops required is
A.	3
B.	5
C.	7
D.	9
Answer» C. 7

Discussion

181.	When a large number of analog signals are to be converted an analog multiplexer is used. In this case most suitable A.D. converter will be
A.	ripple carry counter type
B.	dual stop type
C.	forward counter type
D.	successive approxima tion type
Answer» E.

Discussion

182.	For which of the following flip-flops, the output is clearly defined for all combinations of two inputs ?
A.	q type flip-flop
B.	r-s flip-lop
C.	j-k flip-lop
D.	d flip-flop
Answer» D. d flip-flop

Discussion

183.	Popular application of flip-flop are
A.	transfer register
B.	shift registers
C.	counters
D.	all of these
Answer» E.

Discussion

184.	A shift register can be used for
A.	digital delay line
B.	serial to parallel conversion
C.	parallel to serial conversion
D.	all of these
Answer» E.

Discussion

185.	A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is ZERO. The minimum number of states required is
A.	0
B.	1
C.	2
D.	none of these
Answer» D. none of these

Discussion

186.	74L5138 chip functions as
A.	decoder/demu ltiplexer
B.	encoder
C.	multiplexer
D.	demultiple xer
Answer» B. encoder

Discussion

187.	The clock signals are used in sequential logic circuits to
A.	tell the time of the day
B.	tell how much time has elapsed since the system was turned on
C.	carry parllel data signals
D.	synchroniz e events in various parts of system
Answer» E.

Discussion

188.	A n-stage ripple counter will count up to
A.	2n
B.	2n-1
C.	n
D.	2n-1
Answer» B. 2n-1

Discussion

189.	The dynamic hazard problem occurs in
A.	combinational circuit alone
B.	sequential circuit only
C.	both (a) and (b)
D.	none of these
Answer» D. none of these

Discussion

190.	A ring counter is same as
A.	up-down counter
B.	parallel- counter
C.	shift register
D.	ripple carry counter
Answer» D. ripple carry counter

Discussion

191.	A pulse train can be delayed by a finite number of clock periods using
A.	a serial-in serial-out shift register
B.	a serial-in parallel-out shift register
C.	both (a) and (b)
D.	a parallel- in parallel- out shift register
Answer» E.

Discussion

192.	How many illegitimate states has synchronous mod-6 counter ?
A.	3
B.	2
C.	1
D.	6
Answer» B. 2

Discussion

193.	A 2 bit binary multiplier can be implemented using
A.	2 input ands only
B.	2 input xors and 4 input and gates only
C.	2 input nors and one xnor gate
D.	nor gates and shift registers
Answer» C. 2 input nors and one xnor gate

Discussion

194.	With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip- flops required ?
A.	3
B.	12
C.	6
D.	8
Answer» D. 8

Discussion

195.	Match List I with List II and select the correct answer form the codes given below the list List I A. A shift register can be B. A multiplexer C. A decoder can List II 1.for parallel to serial conversion 2.to generate memory can be used chip select 3.for parallel to serial conversion CODES: A B C
A.	3 1 2
B.	2 3 1
C.	1 3 2
D.	1 2 3
Answer» D. 1 2 3

Discussion

196.	Which of the following conditions must be met to avoid race around problem ?
A.	Î” t < tp < t
B.	t > Î”t > tp
C.	2 tp < Î”t < t
D.	none of these
Answer» C. 2 tp < Î”t < t

Discussion

197.	A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now
A.	change its state at each clock pulse
B.	go to state 1 and stay there
C.	go to state 0 and stay there
D.	retain its present state
Answer» B. go to state 1 and stay there

Discussion

198.	12: In a digital counter circuit feedback loop is introduced to
A.	improve distortion
B.	improve stability
C.	reduce the number of input pulses to reset the counter
D.	asynchron ous input and output pulses
Answer» D. asynchron ous input and output pulses

Discussion

199.	The ring counter is analogous to
A.	toggle switch
B.	latch
C.	stepping switch
D.	j-k flip- flop
Answer» D. j-k flip- flop

Discussion

200.	The output of a sequential circuit depends on
A.	present inputs only
B.	past outputs only
C.	both present and past inputs
D.	present outputs only
Answer» D. present outputs only

Discussion

Explore topic-wise MCQs in Computer Science Engineering (CSE).

A decade counter is .

The input overrides the input

The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.

74HC163 has two enable input pins which are and

In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

In a sequential circuit the next state is determined by and

A 8-bit serial in / parallel out shift register contains the value â€œ8â€, Â Â Â Â Â Â Â Â Â clock signal(s) will be required to shift the value completely out of the register.

The number of flip-flops required in a decade counter is

Register is a

If in a shift resistor Q0 is fed back to input the resulting counter is

If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

If the input J is connected through K input of J-K, then flip-flop will behave as a

Which of the following flip-flop is free from race-around problem ?

Which of the following unit will choose to transform decimal number to binary code ?

The flip-flops which operate in synchronism with external clock pulses are known as

The main difference between JK and RS flip-flop is that

41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the

How many flip-flop are needed to divide the input frequency by 64 ?

The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is

It is difficult to design asynhronous sequential circuit because

The master slave JK lip-flop is effectively a combination of

A stable multivibrator is used as

The functional difference between S-R flip-flop and J-K flip-flop is that J- K flip-flop

A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be

When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is

In a positive edge triggered JK flip-flop, a low J and low K produces

How many bits are required to encode all twenty six letters, ten symbols, and ten numerals ?

The astable multivibrator has

To build a mod-19 counter the number of flip-flops required is

When a large number of analog signals are to be converted an analog multiplexer is used. In this case most suitable A.D. converter will be

For which of the following flip-flops, the output is clearly defined for all combinations of two inputs ?

Popular application of flip-flop are

A shift register can be used for

A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is ZERO. The minimum number of states required is

74L5138 chip functions as

The clock signals are used in sequential logic circuits to

A n-stage ripple counter will count up to

The dynamic hazard problem occurs in

A ring counter is same as

A pulse train can be delayed by a finite number of clock periods using

How many illegitimate states has synchronous mod-6 counter ?

A 2 bit binary multiplier can be implemented using

With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip- flops required ?

Match List I with List II and select the correct answer form the codes given below the list List I A. A shift register can be B. A multiplexer C. A decoder can List II 1.for parallel to serial conversion 2.to generate memory can be used chip select 3.for parallel to serial conversion CODES: A B C

Which of the following conditions must be met to avoid race around problem ?

A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now

12: In a digital counter circuit feedback loop is introduced to

The ring counter is analogous to

The output of a sequential circuit depends on

A 8-bit serial in / parallel out shift register contains the value â€œ8â€, Â Â Â Â Â Â Â Â Â clock signal(s) will be required to shift the value completely out of the register.