646 + Mcqs in Digital Electronics And Logic Design Page 5 McqOptions

201.	9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output
A.	q will flip from 0 to 1 and then back to 0
B.	q will flip from 0 to 1 and then back to 0
C.	q will flip from 1 to 0
D.	q will flip from 0 to 1
Answer» E.

Discussion

202.	8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now
A.	change its state at each clock pulse
B.	go to state 1 and stay there
C.	go to state 0 and stay there
D.	retain its previous state
Answer» E.

Discussion

203.	What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ?
A.	1 mhz
B.	10 mhz
C.	100 mhz
D.	8 mhz
Answer» C. 100 mhz

Discussion

204.	A mod-2 counter followed by a mod-5 counter is
A.	same as a mode-5 counter followed by a mod- 2 counter
B.	a decade counter
C.	a mod-7 counter
D.	ripple carry counter
Answer» B. a decade counter

Discussion

205.	4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip-lops ? Assume unlimited fan-in.
A.	6
B.	3
C.	2
D.	1
Answer» D. 1

Discussion

206.	5: The clear data and present input of the JK lip-lop are known as
A.	synchronous inputs
B.	directed inputs
C.	either (a) or (b)
D.	none of thes
Answer» D. none of thes

Discussion

207.	3: Flip-flop outputs are always
A.	complimentary
B.	the same
C.	independent of each other
D.	same as previous input
Answer» B. the same

Discussion

208.	2: The number of flip-flops required in a modulo N counter is
A.	log2 (n) + 1
B.	log2(n-1)
C.	log2 (n)
D.	n log2 (n)
Answer» D. n log2 (n)

Discussion

209.	1: When the maximum clock rate is quoted for a logic family, then it applies to a
A.	shift register
B.	flip-flop
C.	counter
D.	multiplexe r
Answer» C. counter

Discussion

210.	An astable has two metastable states and produces the function of a digital oscillator
A.	true
B.	false
Answer» B. false

Discussion

211.	In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time.
A.	true
B.	false
Answer» B. false

Discussion

212.	Which of the following is not a form of multivibrator?
A.	astable.
B.	monostable.
C.	tristable.
D.	bistable.
Answer» D. bistable.

Discussion

213.	A combinatorial logic circuit has memory characteristics that "remember" the inputs after they have been removed.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

214.	A master/slave bistable is formed using two bistable connected in series.
A.	true
B.	false
Answer» B. false

Discussion

215.	A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?
A.	the q output toggles to the other state.
B.	the q output is set to 1.
C.	the q output is reset to 0.
D.	the q output remains unchanged .
Answer» B. the q output is set to 1.

Discussion

216.	In true sum-of-products expressions, the inversion signs cannot cover more than single variables in a term.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

217.	An encoder in which the highest and lowest value input digits are encoded simultaneously is known as a priority encoder.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

218.	Single looping in groups of three is a common K-map simplification technique.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

219.	Three select lines are required to address four data input lines.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

220.	The CASE control structure is used when an expression has a list of possible values.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

221.	The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

222.	An exclusive-OR gate will invert a signal on one input if the other is always HIGH.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

223.	A digital circuit that converts coded information into a familiar or non- coded form is known as an encoder.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

224.	A data selector is also called a demultiplexer.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

225.	A pull-up resistor is a resistor used to keep a given point in a circuit HIGH when in the active state.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

226.	The look-ahead carry method suffers from propagation delays.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

227.	Even parity is the condition of having an even number of 1s in every group of bits.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

228.	The K-map provides a "graphical" approach to simplifying sum-of- products expressions.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

229.	When decisions demand one of many possible actions, the ELSIF control structure is used.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

230.	The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

231.	The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

232.	In an even-parity system, the parity bit is adjusted to make an even number of one bits.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

233.	In an even-parity system, the following data will produce a parity bit = 1. data = 1010011
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

234.	The abbreviation for an exclusive-OR gate is XOR.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

235.	This is an example of a POS expression:
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

236.	The 54 prefix on ICs indicates a broader operating temperature range, generally intended for military use.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

237.	TTL stands for transistor-technology-logic.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

238.	When decisions demand two possible actions, the IF/THEN/ELSE control structure is used.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

239.	The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

240.	To implement the full-adder sum functions, two exclusive-OR gates can be used.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

241.	A square in the top row of a K-map is considered to be adjacent to its corresponding square in the bottom row.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

242.	Truth tables are great for listing all possible combinations of independent variables.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

243.	The carry output of each adder in a ripple adder provides an additional sum output bit.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

Discussion

244.	A good rule of thumb for determining the pin numbers of dual-in-line package IC chips would be to place the notch to your right and pin #1 will always be in the lower right corner.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

245.	Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â or , in order to the resulting term.
A.	don\t care, 1\s, 0\s, simplify
B.	spurious, and\s, or\s, eliminate
C.	duplicate, 1\s, 0\s, verify
D.	spurious, 1\s, 0\s, simplify
Answer» B. spurious, and\s, or\s, eliminate

Discussion

246.	The circuit produces a HIGH output whenever the two inputs are unequal.
A.	exclusive-and
B.	exclusive- nor
C.	exclusive-or
D.	inexclusive -or
Answer» D. inexclusive -or

Discussion

247.	When grouping cells within a K-map, the cells must be combined in groups of .
A.	2\s
B.	1, 2, 4, 8, etc.
C.	4\s
D.	3\s
Answer» C. 4\s

Discussion

248.	In VHDL, data can be each of the following types except .
A.	bit
B.	bit_vector
C.	std_logic
D.	std_vect or
Answer» E.

Discussion

249.	The statement evaluates the variable status.
A.	if/then
B.	if/then/el se
C.	case
D.	elsif
Answer» B. if/then/el se

Discussion

250.	A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be .
A.	1100
B.	10101
C.	11000
D.	11
Answer» D. 11

Discussion

Explore topic-wise MCQs in Computer Science Engineering (CSE).

9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output

8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now

What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ?

A mod-2 counter followed by a mod-5 counter is

4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip-lops ? Assume unlimited fan-in.

5: The clear data and present input of the JK lip-lop are known as

3: Flip-flop outputs are always

2: The number of flip-flops required in a modulo N counter is

1: When the maximum clock rate is quoted for a logic family, then it applies to a

An astable has two metastable states and produces the function of a digital oscillator

In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time.

Which of the following is not a form of multivibrator?

A combinatorial logic circuit has memory characteristics that "remember" the inputs after they have been removed.

A master/slave bistable is formed using two bistable connected in series.

A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?

In true sum-of-products expressions, the inversion signs cannot cover more than single variables in a term.

An encoder in which the highest and lowest value input digits are encoded simultaneously is known as a priority encoder.

Single looping in groups of three is a common K-map simplification technique.

Three select lines are required to address four data input lines.

The CASE control structure is used when an expression has a list of possible values.

The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0

An exclusive-OR gate will invert a signal on one input if the other is always HIGH.

A digital circuit that converts coded information into a familiar or non- coded form is known as an encoder.

A data selector is also called a demultiplexer.

A pull-up resistor is a resistor used to keep a given point in a circuit HIGH when in the active state.

The look-ahead carry method suffers from propagation delays.

Even parity is the condition of having an even number of 1s in every group of bits.

The K-map provides a "graphical" approach to simplifying sum-of- products expressions.

When decisions demand one of many possible actions, the ELSIF control structure is used.

The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.

The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0

In an even-parity system, the parity bit is adjusted to make an even number of one bits.

In an even-parity system, the following data will produce a parity bit = 1. data = 1010011

The abbreviation for an exclusive-OR gate is XOR.

This is an example of a POS expression:

The 54 prefix on ICs indicates a broader operating temperature range, generally intended for military use.

TTL stands for transistor-technology-logic.

When decisions demand two possible actions, the IF/THEN/ELSE control structure is used.

The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.

To implement the full-adder sum functions, two exclusive-OR gates can be used.

A square in the top row of a K-map is considered to be adjacent to its corresponding square in the bottom row.

Truth tables are great for listing all possible combinations of independent variables.

The carry output of each adder in a ripple adder provides an additional sum output bit.

A good rule of thumb for determining the pin numbers of dual-in-line package IC chips would be to place the notch to your right and pin #1 will always be in the lower right corner.

Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â or , in order to the resulting term.

The circuit produces a HIGH output whenever the two inputs are unequal.

When grouping cells within a K-map, the cells must be combined in groups of .

In VHDL, data can be each of the following types except .

The statement evaluates the variable status.

A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be .