MCQOPTIONS
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MCQOPTIONS
This section includes 646 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
In asynchronous digital systems all the circuits change their state with respect to a common clock |
| A. | true |
| B. | false |
| Answer» C. | |
| 102. |
The low to high or high to low transition of the clock is considered to be a(n) |
| A. | state |
| B. | edge |
| C. | trigger |
| D. | one-shot |
| Answer» C. trigger | |
| 103. |
RCO Stands for |
| A. | reconfiguratio n counter output |
| B. | reconfigurati on clock output |
| C. | ripple counter output |
| D. | ripple clock output |
| Answer» E. | |
| 104. |
Bi-stable devices remain in either of their states unless the inputs force the device to switch its state |
| A. | ten |
| B. | eight |
| C. | three |
| D. | two |
| Answer» E. | |
| 105. |
                    is one of the examples of asynchronous inputs. |
| A. | j-k input |
| B. | s-r input |
| C. | d input |
| D. | clear input (clr) |
| Answer» E. | |
| 106. |
                 occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 107. |
A transparent mode means |
| A. | the changes in the data at the inputs of the latch are seen at the output |
| B. | the changes in the data at the inputs of the latch are not seen at the output |
| C. | propagation delay is zero (output is immediately changed when clock signal is applied) |
| D. | input hold time is zero (no need to maintain input after clock transition) |
| Answer» B. the changes in the data at the inputs of the latch are not seen at the output | |
| 108. |
The alternate solution for a demultiplexer-register combination circuit is |
| A. | parallel in / serial out shift register |
| B. | serial in / parallel out shift register |
| C. | parallel in / parallel out shift register |
| D. | serial in / serial out shift register |
| Answer» C. parallel in / parallel out shift register | |
| 109. |
The sequence of states that are implemented by a n-bit Johnson counter is |
| A. | n+2 (n plus 2) |
| B. | 2n (n multiplied by 2) |
| C. | 2n (2 raise to power n) |
| D. | n2 (n raise to power 2) |
| Answer» C. 2n (2 raise to power n) | |
| 110. |
A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1? |
| A. | = 0, cout = 0 |
| B. | = 0, cout = 1 |
| C. | ï€ = 1, cout = 0 |
| D. | ï€ = 1, cout = 1 |
| Answer» C. ï€ = 1, cout = 0 | |
| 111. |
A particular half adder has |
| A. | 2 inputs and 1 output |
| B. | 2 inputs and 2 output |
| C. | 3 inputs and 1 output |
| D. | 3 inputs and 2 output |
| Answer» C. 3 inputs and 1 output | |
| 112. |
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â GATE |
| A. | and |
| B. | or |
| C. | nand |
| D. | xor |
| Answer» C. nand | |
| 113. |
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 114. |
Flip flops are also called |
| A. | bi-stable dualvibrators |
| B. | bi-stable transformer |
| C. | bi-stable multivibrator s |
| D. | bi-stable singlevibra tors |
| Answer» D. bi-stable singlevibra tors | |
| 115. |
A positive edge-triggered flip-flop changes its state when |
| A. | low-to-high transition of clock |
| B. | high-to-low transition of clock |
| C. | enable input (en) is set |
| D. | preset input (pre) is set |
| Answer» B. high-to-low transition of clock | |
| 116. |
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A |
| A. | gated flip- flops |
| B. | pulse triggered flip-flops |
| C. | positive- edge triggered flip-flops |
| D. | negative -edge triggere d flip- flops |
| Answer» E. | |
| 117. |
The design and implementation of synchronous counters start from |
| A. | truth table |
| B. | k-map |
| C. | state table |
| D. | state diagram |
| Answer» E. | |
| 118. |
THE HOURS COUNTER IS IMPLEMENTED USING |
| A. | only a single mod- 12 counter is required |
| B. | mod-10 and mod-6 counters |
| C. | mod-10 and mod-2 counters |
| D. | a single decade counter and a flip-flop |
| Answer» E. | |
| 119. |
Given the state diagram of an up/down counter, we can find |
| A. | the next state of a given present state |
| B. | the previous state of a given present state |
| C. | both the next and previous states of a given state |
| D. | the state diagram shows only the inputs/out puts of a given states |
| Answer» B. the previous state of a given present state | |
| 120. |
In outputs depend only on the current state. |
| A. | mealy machine |
| B. | moore machine |
| C. | state reduction table |
| D. | state assignmen t table |
| Answer» C. state reduction table | |
| 121. |
The alternate solution for a multiplexer and a register circuit is |
| A. | parallel in / serial out shift register |
| B. | serial in / parallel out shift register |
| C. | parallel in / parallel out shift register |
| D. | serial in / serial out shift register |
| Answer» B. serial in / parallel out shift register | |
| 122. |
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1â€. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 123. |
A synchronous decade counter will have flip-flops |
| A. | 3 |
| B. | 4 |
| C. | 7 |
| D. | 10 |
| Answer» C. 7 | |
| 124. |
A 8-bit serial in / parallel out shift register contains the value “8â€,          clock signal(s) will be required to shift the value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 125. |
5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES |
| A. | 7 |
| B. | 10 |
| C. | 32 |
| D. | 25 |
| Answer» C. 32 | |
| 126. |
In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. |
| A. | moore machine |
| B. | meally machine |
| C. | johnson counter |
| D. | ring counter |
| Answer» E. | |
| 127. |
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO ------- |
| A. | the flop- flop is triggered |
| B. | q=0 and q‟=1 |
| C. | q=1 and q‟=0 |
| D. | the output of flip- flop remains unchang ed |
| Answer» E. | |
| 128. |
The characteristic equation of a JK flip flop is |
| A. | qn+1=j.qn+k.q n |
| B. | qn+1=j.q’n+ k’.qn |
| C. | qn+1=qnj.k |
| D. | qn+1=(j+k )qn |
| Answer» C. qn+1=qnj.k | |
| 129. |
Advantage of synchronous sequential circuits over asynchronous ones is |
| A. | faster operation |
| B. | ease of avoiding problems due to hazard |
| C. | lower hardware requirement |
| D. | better noise immunity |
| Answer» B. ease of avoiding problems due to hazard | |
| 130. |
A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is |
| A. | 18 |
| B. | 9 |
| C. | 5 |
| D. | 4 |
| Answer» D. 4 | |
| 131. |
How many flip-flops are required to produce a divide-by-32 device? |
| A. | 2 |
| B. | 5 |
| C. | 6 |
| D. | 4 |
| Answer» C. 6 | |
| 132. |
in , all the columns in the same row are either read or written. |
| A. | sequential access |
| B. | mos access |
| C. | fast mode page access |
| D. | none of given options |
| Answer» D. none of given options | |
| 133. |
A GAL is essentially a . |
| A. | non- reprogrammab le pal |
| B. | pal that is programmed only by the manufacture r |
| C. | very large pal |
| D. | reprogra mmable pal |
| Answer» E. | |
| 134. |
A multiplexer with a register circuit converts |
| A. | serial data to parallel |
| B. | parallel data to serial |
| C. | serial data to serial |
| D. | parallel data to parallel |
| Answer» C. serial data to serial | |
| 135. |
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop |
| A. | doesn’t have an invalid state |
| B. | sets to clear when both j = 0 and k = 0 |
| C. | it does not show transition on change in pulse |
| D. | it does not accept asynchron ous inputs |
| Answer» B. sets to clear when both j = 0 and k = 0 | |
| 136. |
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) |
| A. | 1100 |
| B. | 11 |
| C. | 1111 |
| Answer» D. | |
| 137. |
The diagram given below represents |
| A. | demorgans law |
| B. | associative law |
| C. | product of sum form |
| D. | sum of product form |
| Answer» E. | |
| 138. |
In a state diagram, the transition from a current state to the next state is determined by |
| A. | current state and the inputs |
| B. | current state and outputs |
| C. | previous state and inputs |
| D. | previous state and outputs |
| Answer» B. current state and outputs | |
| 139. |
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0†the counter counts upward (0000 to 1111) and if external input (X) is “1†the counter counts downward (1111 to 0000), now suppose that the present state is “1100†and X=1, the next state of the counter will be |
| A. | 0 |
| B. | 1101 |
| C. | 1011 |
| D. | 1111 |
| Answer» C. 1011 | |
| 140. |
                 occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 141. |
               is used to simplify the circuit that determines the next state. |
| A. | state diagram |
| B. | next state table |
| C. | state reduction |
| D. | state assignmen t |
| Answer» E. | |
| 142. |
The voltage gain of the Inverting Amplifier is given by the relation |
| A. | vout / vin = - rf / ri |
| B. | vout / rf = - vin / ri |
| C. | rf / vin = - ri / vout |
| D. | rf / vin = ri / vout |
| Answer» B. vout / rf = - vin / ri | |
| 143. |
Stack is an acronym for |
| A. | fifo memory |
| B. | lifo memory |
| C. | flash memory |
| D. | bust flash memory |
| Answer» C. flash memory | |
| 144. |
The three fundamental gates are |
| A. | and, nand, xor |
| B. | or, and, nand |
| C. | not, nor, xor |
| D. | not, or, and |
| Answer» E. | |
| 145. |
LUT is acronym for |
| A. | look up table |
| B. | local user terminal |
| C. | least upper time period |
| D. | none of given options |
| Answer» B. local user terminal | |
| 146. |
                    is one of the examples of synchronous inputs. |
| A. | j-k input |
| B. | en input |
| C. | preset input (pre) |
| D. | clear input (clr) |
| Answer» B. en input | |
| 147. |
The output of this circuit is always . |
| A. | 1 |
| B. | 0 |
| C. | a |
| D. | abar |
| Answer» D. abar | |
| 148. |
A Nibble consists of bits |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» C. 8 | |
| 149. |
In asynchronous transmission when the transmission line is idle, |
| A. | it is set to logic low |
| B. | it is set to logic high |
| C. | remains in previous state |
| D. | state of transmissi on line is not used to start transmissi on |
| Answer» C. remains in previous state | |
| 150. |
to change in one input variable |
| A. | clock skew |
| B. | condition |
| C. | hold delay |
| D. | wait |
| Answer» C. hold delay | |