MCQOPTIONS
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MCQOPTIONS
This section includes 646 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 52. |
DeMorgan’s first theorem shows the equivalence of |
| A. | or gate and exclusive or gate. |
| B. | nor gate and bubbled and gate. |
| C. | nor gate and nand gate. |
| D. | nandgate and not gate |
| Answer» C. nor gate and nand gate. | |
| 53. |
The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) |
| A. | and/or |
| B. | nand |
| C. | nor |
| D. | or/and |
| Answer» C. nor | |
| 54. |
The AND-OR-INVERT gates are designed to simplify implementation of. |
| A. | pos logic |
| B. | demorgan\s theorem |
| C. | nand logic |
| D. | sop logic |
| Answer» C. nand logic | |
| 55. |
Parity generators and checkers use gates. |
| A. | exclusive-and |
| B. | exclusive- or/nor |
| C. | exclusive-or |
| D. | exclusive- nand |
| Answer» C. exclusive-or | |
| 56. |
Addition of two octal numbers “36” and “71” results in |
| A. | 213 |
| B. | 123 |
| C. | 127 |
| D. | 345 |
| Answer» D. 345 | |
| 57. |
is one of the examples of asynchronous inputs. |
| A. | j-k input |
| B. | s-r input |
| C. | d input |
| D. | clear input (clr) |
| Answer» E. | |
| 58. |
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter countsupward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), nowsuppose that the present state is “1100” and X=1, the next state of the counter will be |
| A. | 0 |
| B. | 1101 |
| C. | 1011 |
| D. | 1111 |
| Answer» C. 1011 | |
| 59. |
The inverter OR-gate and AND gate are called deeision-making elementsbecause they can recognize some input while disregarding others. A gate |
| A. | words,high |
| B. | bytes,low |
| C. | bytes,high |
| D. | character,low |
| Answer» B. bytes,low | |
| 60. |
Minimize the logic functionY(A,B,C,D) = IZm(0,1,2,3,5,7,8,9,11,14) . UsingKarnaugh map. |
| A. | abc d\ + a\ b\+ b\ c\ + b\ d+ a\d |
| B. | abc d + a b+ b\ c\ + b\ d+ a\d |
| C. | a\ b\ + b\ c\ + b\ d+ a\d |
| D. | abc d\ + a\ b\ + b\ c\ + b\ d |
| Answer» B. abc d + a b+ b\ c\ + b\ d+ a\d | |
| 61. |
The decimal “17” in BCD will be represented as 10001(right opt is not given) |
| A. | 11101 |
| B. | 11011 |
| C. | 10111 |
| D. | 11110 |
| Answer» D. 11110 | |
| 62. |
occurs when the same clock signal arrives at different times at different clock inputs due topropagation delay. |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 63. |
Match List I with List II and select the correct answer form the codes given below the list List IA. A shift register can beB. A multiplexerC. A decoder can List II 1.for parallel to serial conversion2.to generate memory can be used chip select 3.for parallel to serial conversionCODES: A B C |
| A. | 3 1 2 |
| B. | 2 3 1 |
| C. | 1 3 2 |
| D. | 1 2 3 |
| Answer» D. 1 2 3 | |
| 64. |
Indicate which of the following three binary additions are correct? 1.1011 + 1010 = 10101II. 1010 + 1101 = 10111III. 1010 + 1101 = 11111 |
| A. | i and ii |
| B. | ii and iii |
| C. | iii only |
| D. | ii and i |
| Answer» E. | |
| 65. |
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUTMULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE |
| A. | and |
| B. | or |
| C. | nand |
| D. | xor |
| Answer» C. nand | |
| 66. |
If the S and R inputs of the gated S-R latch are connected together using a gate then there is only asingle input to the latch. The input is represented by D instead of S or R (A gated D-Latch) |
| A. | and |
| B. | or |
| C. | not |
| D. | xor |
| Answer» D. xor | |
| 67. |
Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either or , in order to the resulting term. |
| A. | don\t care, 1\s, 0\s, simplify |
| B. | spurious, and\s, or\s,eliminate |
| C. | duplicate, 1\s, 0\s, verify |
| D. | spurious, 1\s, 0\s,simplify |
| Answer» B. spurious, and\s, or\s,eliminate | |
| 68. |
Add 20 and (-15) using 2’s complement. |
| A. | (100100 )2 or(+4)10 |
| B. | (000100 )2or (-4)10 |
| C. | both (a) and (b) |
| D. | none of the above |
| Answer» B. (000100 )2or (-4)10 | |
| 69. |
VHDL is very strict in the way it allows us to assign and compare such as signals, variables, constants, and literals. |
| A. | objects |
| B. | logic_vect ors |
| C. | designs |
| D. | arrays |
| Answer» B. logic_vect ors | |
| 70. |
1’s complement representation of decimal number of -17 by using 8 bit |
| A. | 1110 1110 |
| B. | 1101 1101 |
| C. | 1100 1100 |
| D. | 0001 0001 |
| Answer» B. 1101 1101 | |
| 71. |
In the following question, match each of the items A, B and C on the left with an approximation item on the rightA. Shift register can be used 1. for code conversionB. A multiplexer can be used 2. to generate memory slipto selectC. A decoder can be used 3. for parallel to serial conversion4. as many to one switch5. for analog to digital conversion |
| A. | a b c1 2 3 |
| B. | a b c3 4 1 |
| C. | a b c5 4 2 |
| D. | a b c1 3 5 |
| Answer» C. a b c5 4 2 | |
| 72. |
5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES |
| A. | 7 |
| B. | 10 |
| C. | 32 |
| D. | 25 |
| Answer» C. 32 | |
| 73. |
Subtraction of 01100-00011 using 2’s complement method. : |
| A. | 1001 |
| B. | 1000 |
| C. | 1010 |
| D. | 110 |
| Answer» B. 1000 | |
| 74. |
is one of the examples of synchronous inputs. |
| A. | j-k input |
| B. | en input |
| C. | preset input (pre) |
| D. | clear input (clr) |
| Answer» B. en input | |
| 75. |
In Q output of the last flip-flop of the shift register is connected to the data input of the firstflip-flop of the shift register. |
| A. | moore machine |
| B. | meally machine |
| C. | johnson counter |
| D. | ring counter |
| Answer» E. | |
| 76. |
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. Whatwill be the 4-bit pattern after the second clock pulse? (Right-most bit first.) |
| A. | 1100 |
| B. | 11 |
| C. | 1111 |
| Answer» D. | |
| 77. |
The Gray code for decimal number 6 is equivalent to |
| A. | 1100 |
| B. | 1001 |
| C. | 101 |
| D. | 110 |
| Answer» D. 110 | |
| 78. |
Convert the binary number 10110 to Gray code: |
| A. | 11101 |
| B. | 11001 |
| C. | 10101 |
| D. | 11100 |
| Answer» B. 11001 | |
| 79. |
A frequency counter |
| A. | counts pulse width |
| B. | counts no. of clock pulses in 1 second |
| C. | counts high and low range of given clock pulse |
| D. | none of given options |
| Answer» C. counts high and low range of given clock pulse | |
| 80. |
What is the difference between a D latch and a D flip-flop? |
| A. | the d latch has a clock input. |
| B. | the d flip- flop has an enable input. |
| C. | ï€ the d latch is used for faster operation. |
| D. | the d flip- flop has a clock input. |
| Answer» E. | |
| 81. |
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH. |
| A. | ï€ toggle |
| B. | set |
| C. | ï€ reset |
| D. | ï€ not change |
| Answer» B. set | |
| 82. |
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be |
| A. | set |
| B. | reset |
| C. | invalid |
| D. | clear |
| Answer» B. reset | |
| 83. |
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO |
| A. | the flop- flop is triggered |
| B. | q=0 and q‟=1 |
| C. | q=1 and q’=0 |
| D. | the output of flip- flop remains unchang ed |
| Answer» D. the output of flip- flop remains unchang ed | |
| 84. |
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by |
| A. | using s-r flop- flop |
| B. | d-flipflop |
| C. | j-k flip-flop |
| D. | t-flip-flop |
| Answer» D. t-flip-flop | |
| 85. |
status. |
| A. | 3 |
| B. | 7 |
| C. | 8 |
| D. | 15 |
| Answer» D. 15 | |
| 86. |
If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | input is invalid |
| Answer» D. input is invalid | |
| 87. |
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = |
| A. | 0 |
| B. | 1 |
| C. | q(t) |
| D. | invalid |
| Answer» C. q(t) | |
| 88. |
In outputs depend only on the combination of current state and inputs |
| A. | mealy machine |
| B. | moore machine |
| C. | state reduction table |
| D. | state assignmen t table |
| Answer» B. moore machine | |
| 89. |
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing . |
| A. | 1110 |
| B. | 111 |
| C. | 1000 |
| D. | 1001 |
| Answer» E. | |
| 90. |
The high density FLASH memory cell is implemented using |
| A. | 1 floating-gate mos transistor |
| B. | 2 floating- gate mos transistors |
| C. | 4 floating- gate mos transistors |
| D. | 6 floating- gate mos transistors |
| Answer» B. 2 floating- gate mos transistors | |
| 91. |
At T0 the value stored in a 4-bit left shift was “1â€. What will be the value of register after three clock pulses? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 92. |
Above is the circuit diagram of |
| A. | asynchronous up-counter |
| B. | asynchronou s down- counter |
| C. | synchronous up-counter |
| D. | synchrono us down- counter |
| Answer» B. asynchronou s down- counter | |
| 93. |
Q2 :=Q1 OR X OR Q3 The above ABEL expression will be |
| A. | q2:= q1 $ x $ q3 |
| B. | q2:= q1 # x # q3 |
| C. | q2:= q1 & x & q3 |
| D. | q2:= q1 ! x ! q3 |
| Answer» C. q2:= q1 & x & q3 | |
| 94. |
The decimal “17†in BCD will be represented as 10001(right opt is not given) |
| A. | 11101 |
| B. | 11011 |
| C. | 10111 |
| D. | 11110 |
| Answer» D. 11110 | |
| 95. |
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 96. |
The simplest and most commonly used Decoders are the Decoders |
| A. | n to 2n |
| B. | (n-1) to 2n |
| C. | (n-1) to (2n- 1) |
| D. | n to 2n-1 |
| Answer» B. (n-1) to 2n | |
| 97. |
The Encoder is used as a keypad encoder. |
| A. | 2-to-8 encoder |
| B. | 4-to-16 encoder |
| C. | bcd-to- decimal |
| D. | decimal- to-bcd priority |
| Answer» E. | |
| 98. |
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions |
| A. | true |
| B. | false |
| Answer» B. false | |
| 99. |
If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | input is invalid |
| Answer» C. invalid | |
| 100. |
If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) |
| A. | and |
| B. | or |
| C. | not |
| D. | xor |
| Answer» D. xor | |