VHDL is very strict in the way it allows us to assign and compare such as signals, variables, constants, and literals.

VHDL is very strict in the way it allows us to assign and compare

1.	VHDL is very strict in the way it allows us to assign and compare such as signals, variables, constants, and literals.
A.	objects
B.	logic_vect ors
C.	designs
D.	arrays
Answer» B. logic_vect ors

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VHDL is very strict in the way it allows us to assign and compare such as signals, variables, constants, and literals.

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