2291 + Mcqs in Digital Electronics Page 34 McqOptions

1651.	The 54 prefix on ICs indicates a broader operating temperature range, generally intended for military use.
A.	True
B.	False
Answer» B. False

Discussion

1652.	This is an example of a POS expression:
A.	True
B.	False
Answer» B. False

Discussion

1653.	A data selector is also called a demultiplexer.
A.	True
B.	False
Answer» C.

Discussion

1654.	An exclusive-OR gate will invert a signal on one input if the other is always HIGH.
A.	True
B.	False
Answer» B. False

Discussion

1655.	TTL stands for transistor-technology-logic.
A.	True
B.	False
Answer» C.

Discussion

1656.	The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0
A.	True
B.	False
Answer» C.

Discussion

1657.	The circuit given below implements the equation, .
A.	True
B.	False
Answer» B. False

Discussion

1658.	The abbreviation for an exclusive-OR gate is XOR.
A.	True
B.	False
Answer» B. False

Discussion

1659.	In an even-parity system, the parity bit is adjusted to make an even number of one bits.
A.	True
B.	False
Answer» B. False

Discussion

1660.	The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.
A.	True
B.	False
Answer» B. False

Discussion

1661.	When decisions demand one of many possible actions, the ELSIF control structure is used.
A.	True
B.	False
Answer» B. False

Discussion

1662.	The CASE control structure is used when an expression has a list of possible values.
A.	True
B.	False
Answer» B. False

Discussion

1663.	In VHDL, data can be each of the following types except ________.
A.	BIT
B.	BIT_VECTOR
C.	STD_LOGIC
D.	STD_VECTOR
Answer» E.

Discussion

1664.	When grouping cells within a K-map, the cells must be combined in groups of ________.
A.	2's
B.	1, 2, 4, 8, etc.
C.	4's
D.	3's
Answer» C. 4's

Discussion

1665.	The ________ circuit produces a HIGH output whenever the two inputs are unequal.
A.	exclusive-AND
B.	exclusive-NOR
C.	exclusive-OR
D.	inexclusive-OR
Answer» D. inexclusive-OR

Discussion

1666.	The Boolean equation ________ results from this Karnaugh map.
A.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1020a1.gif" align="center">
B.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1020b1.gif" align="center">
C.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1020c1.gif" align="center">
D.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1020d1.gif" align="center">
Answer» B. <img src="/_files/images/digital-electronics/digital-systems/fba4_1020b1.gif" align="center">

Discussion

1667.	The ________ series of IC's are pin, function, and voltage-level compatible with the 74 series IC's.
A.	ALS
B.	CMOS
C.	HCT
D.	2N
Answer» D. 2N

Discussion

1668.	The simplified form of is ________.
A.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1015a1.jpeg">
B.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1015b1.jpeg">
C.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1015c1.jpeg">
D.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1015d1.jpeg">
Answer» E.

Discussion

1669.	The ________ circuit produces a HIGH output whenever the two inputs are equal.
A.	exclusive-AND
B.	exclusive-NAND
C.	exclusive-NOR
D.	exclusive-OR
Answer» D. exclusive-OR

Discussion

1670.	A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________.
A.	01100
B.	10101
C.	11000
D.	00011
Answer» D. 00011

Discussion

1671.	The ________ statement evaluates the variable status.
A.	IF/THEN
B.	IF/THEN/ELSE
C.	CASE
D.	ELSIF
Answer» B. IF/THEN/ELSE

Discussion

1672.	An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if ________.
A.	the number is odd
B.	the number of 1s in the number is odd
C.	the number is even
D.	the number of 1s in the number is even
Answer» E.

Discussion

1673.	Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected ________.
A.	to the outputs from the least significant 4-bit comparator
B.	to the cascading inputs of the least significant 4-bit comparator
C.	A = B to a logic high, A < b and a > B to a logic low
D.	ground
Answer» B. to the cascading inputs of the least significant 4-bit comparator

Discussion

1674.	When Karnaugh mapping, we must be sure to use the ________ number of loops.
A.	maximum
B.	minimum
C.	median
D.	Karnaugh
Answer» C. median

Discussion

1675.	The final output of a POS circuit is generated by ________.
A.	an AND
B.	an OR
C.	a NOR
D.	a NAND
Answer» B. an OR

Discussion

1676.	The correct output for this XOR truth table is ________.
A.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1022a1.gif" align="center">
B.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1022b1.gif" align="center">
C.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1022c1.gif" align="center">
D.	<img src="/_files/images/digital-electronics/digital-systems/fba4_1022d1.gif" align="center">
Answer» E.

Discussion

1677.	In an odd-parity system, the data that will produce a parity bit = 1 is ________.
A.	data = 1010011
B.	data = 1111000
C.	data = 1100000
D.	All of the above
Answer» E.

Discussion

1678.	Except for ________, STD_LOGIC may have the following values.
A.	'z'
B.	'U'
C.	'?'
D.	'L'
Answer» D. 'L'

Discussion

1679.	A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) ________.
A.	XOR gate
B.	XNOR gate
C.	NAND gate
D.	NOR gate
Answer» C. NAND gate

Discussion

1680.	VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals.
A.	objects
B.	LOGIC_VECTORS
C.	designs
D.	arrays
Answer» B. LOGIC_VECTORS

Discussion

1681.	The AND-OR-INVERT gates are designed to simplify implementation of ________.
A.	POS logic
B.	DeMorgan's theorem
C.	NAND logic
D.	SOP logic
Answer» C. NAND logic

Discussion

1682.	If you need a NAND, an AND, and an inverter you would purchase a 7400 IC.
A.	True
B.	False
Answer» B. False

Discussion

1683.	The systematic reduction of logic circuits is performed using Boolean algebra.
A.	True
B.	False
Answer» B. False

Discussion

1684.	CPLD software can be used to design original circuits that prove the Boolean rules and laws.
A.	True
B.	False
Answer» B. False

Discussion

1685.	A Karnaugh map is similar to a truth table.
A.	True
B.	False
Answer» B. False

Discussion

1686.	Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in ________ terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term.
A.	don't care, 1's, 0's, simplify
B.	spurious, AND's, OR's, eliminate
C.	duplicate, 1's, 0's, verify
D.	spurious, 1's, 0's, simplify
Answer» B. spurious, AND's, OR's, eliminate

Discussion

1687.	After each circuit in a subsection of a VHDL program has been ________, they can be combined and the subsection can be tested.
A.	designed
B.	tested
C.	engineered
D.	produced
Answer» C. engineered

Discussion

1688.	A Karnaugh map will ________.
A.	eliminate the need for tedious Boolean simplifications
B.	allow any circuit to be implemented with just AND and OR gates
C.	produce the simplest sum-of-products expression
D.	give an overall picture of how the signals flow through the logic circuit
Answer» B. allow any circuit to be implemented with just AND and OR gates

Discussion

1689.	The symbol shown below is for a 2-input NAND gate.
A.	True
B.	False
Answer» C.

Discussion

1690.	SOP stands for sum-of-powers.
A.	True
B.	False
Answer» C.

Discussion

1691.	The VHDL editor provided with a schematic editor development system will produce a file with the extension .vhd, which can be used by the simulator to test the output of the logic design.
A.	True
B.	False
Answer» B. False

Discussion

1692.	In the commutative law, in ORing and ANDing of two variables, the order in which the variables are ORed or ANDed makes no difference.
A.	True
B.	False
Answer» B. False

Discussion

1693.	The binary value of 1010 is converted to the product term .
A.	True
B.	False
Answer» C.

Discussion

1694.	Most Boolean reductions result in an equation in only one form.
A.	True
B.	False
Answer» C.

Discussion

1695.	Boolean algebra simplifies logic circuits.
A.	True
B.	False
Answer» B. False

Discussion

1696.	The Boolean expression is equal to ________.
A.	C
B.	D
C.	C + D
D.	1
Answer» D. 1

Discussion

1697.	The Boolean expression can be reduced to ________.
A.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua4_0070a.gif">
B.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua4_0070b.gif">
C.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua4_0070c.gif">
D.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua4_0070d.gif">
Answer» E.

Discussion

1698.	Generally speaking, DACs with a current output will have a shorter settling time than those with voltage outputs.
A.	True
B.	False
Answer» B. False

Discussion

1699.	A D/A converter changes things such as temperature variations into digital quantities.
A.	True
B.	False
Answer» C.

Discussion

1700.	The primary disadvantage of the flash A/D converter is the large number of comparators required.
A.	True
B.	False
Answer» B. False

Discussion

Explore topic-wise MCQs in Engineering.

The 54 prefix on ICs indicates a broader operating temperature range, generally intended for military use.

This is an example of a POS expression:

A data selector is also called a demultiplexer.

An exclusive-OR gate will invert a signal on one input if the other is always HIGH.

TTL stands for transistor-technology-logic.

The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0

The circuit given below implements the equation, .

The abbreviation for an exclusive-OR gate is XOR.

In an even-parity system, the parity bit is adjusted to make an even number of one bits.

The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.

When decisions demand one of many possible actions, the ELSIF control structure is used.

The CASE control structure is used when an expression has a list of possible values.

In VHDL, data can be each of the following types except ________.

When grouping cells within a K-map, the cells must be combined in groups of ________.

The ________ circuit produces a HIGH output whenever the two inputs are unequal.

The Boolean equation ________ results from this Karnaugh map.

The ________ series of IC's are pin, function, and voltage-level compatible with the 74 series IC's.

The simplified form of is ________.

The ________ circuit produces a HIGH output whenever the two inputs are equal.

A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________.

The ________ statement evaluates the variable status.

An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if ________.

Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected ________.

When Karnaugh mapping, we must be sure to use the ________ number of loops.

The final output of a POS circuit is generated by ________.

The correct output for this XOR truth table is ________.

In an odd-parity system, the data that will produce a parity bit = 1 is ________.

Except for ________, STD_LOGIC may have the following values.

A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) ________.

VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals.

The AND-OR-INVERT gates are designed to simplify implementation of ________.

If you need a NAND, an AND, and an inverter you would purchase a 7400 IC.

The systematic reduction of logic circuits is performed using Boolean algebra.

CPLD software can be used to design original circuits that prove the Boolean rules and laws.

A Karnaugh map is similar to a truth table.

Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in ________ terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term.

After each circuit in a subsection of a VHDL program has been ________, they can be combined and the subsection can be tested.

A Karnaugh map will ________.

The symbol shown below is for a 2-input NAND gate.

SOP stands for sum-of-powers.

The VHDL editor provided with a schematic editor development system will produce a file with the extension .vhd, which can be used by the simulator to test the output of the logic design.

In the commutative law, in ORing and ANDing of two variables, the order in which the variables are ORed or ANDed makes no difference.

The binary value of 1010 is converted to the product term .

Most Boolean reductions result in an equation in only one form.

Boolean algebra simplifies logic circuits.

The Boolean expression is equal to ________.

The Boolean expression can be reduced to ________.

Generally speaking, DACs with a current output will have a shorter settling time than those with voltage outputs.

A D/A converter changes things such as temperature variations into digital quantities.

The primary disadvantage of the flash A/D converter is the large number of comparators required.

Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either or , in order to the resulting term.