VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals.

VHDL is very strict in the way it allows us to assign and compare ____

1.	VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals.
A.	objects
B.	LOGIC_VECTORS
C.	designs
D.	arrays
Answer» B. LOGIC_VECTORS