MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 701. |
For better transfer rates on the SCSI BUS the length of the cable is limited to |
| A. | 2m |
| B. | 4m |
| C. | 1.3m |
| D. | 1.6m |
| Answer» E. | |
| 702. |
A narrow SCSI BUS has            data lines. |
| A. | 6 |
| B. | 8 |
| C. | 16 |
| D. | 4 |
| Answer» C. 16 | |
| 703. |
           is used to reset all the device controls to their startup state. |
| A. | srt |
| B. | rst |
| C. | atn |
| D. | none of the mentioned |
| Answer» C. atn | |
| 704. |
The MSG signal is used |
| A. | to send a message to the target |
| B. | to receive a message from the mailbox |
| C. | to tell that the information being sent is a message |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 705. |
                  signal is asserted when the initiator wishes to send a message to the target. |
| A. | msg |
| B. | app |
| C. | sms |
| D. | atn |
| Answer» E. | |
| 706. |
The BSY signal signifies |
| A. | the bus is busy |
| B. | the controller is busy |
| C. | the initiator is busy |
| D. | the target is busy |
| Answer» B. the controller is busy | |
| 707. |
What is DB(P) line? |
| A. | that the data line is carrying the device information |
| B. | that the data line is carrying the parity information |
| C. | that the data line is partly closed |
| D. | that the data line is temporarily occupied |
| Answer» C. that the data line is partly closed | |
| 708. |
The SEL signal signifies |
| A. | the initiator is selected |
| B. | the device for bus control is selected |
| C. | that the target is being selected |
| D. | none of the mentioned |
| Answer» C. that the target is being selected | |
| 709. |
In a data transfer operation involving SCSI BUS, the control is with |
| A. | initiator |
| B. | target |
| C. | scsi controller |
| D. | target controller |
| Answer» E. | |
| 710. |
The key features of the SCSI BUS are |
| A. | the cost effective connective media |
| B. | the ability overlap data transfer requests |
| C. | the highly efficient data transmission |
| D. | none of the mentioned |
| Answer» C. the highly efficient data transmission | |
| 711. |
The signal used to initiate device select |
| A. | irdy# |
| B. | s/be |
| C. | devsel# |
| D. | idsel# |
| Answer» E. | |
| 712. |
In SCSI transfers the processor is not aware of the data being transferred. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 713. |
DEVSEL# signal is used |
| A. | to select the device |
| B. | to list all the devices connected |
| C. | by the device to indicate that it is ready for a transaction |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 714. |
The signal used to indicate that the slave is ready is |
| A. | slry# |
| B. | trdy# |
| C. | dsdy# |
| D. | none of the mentioned |
| Answer» C. dsdy# | |
| 715. |
IRDY# signal is used for |
| A. | selecting the interrupt line |
| B. | sending an interrupt |
| C. | saying that the initiator is ready |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 716. |
              signal is used to enable commands. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | c/be# |
| Answer» E. | |
| 717. |
The PCI BUS has            interrupt request lines. |
| A. | 6 |
| B. | 1 |
| C. | 4 |
| D. | 3 |
| Answer» D. 3 | |
| 718. |
           signal is sent by the initiator to indicate the duration of the transaction. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | seld# |
| Answer» B. irdy# | |
| 719. |
The device connected to the BUS are given addresses of          bit. |
| A. | 24 |
| B. | 64 |
| C. | 32 |
| D. | 16 |
| Answer» C. 32 | |
| 720. |
Signals whose names end in          are asserted in the low voltage state. |
| A. | $ |
| B. | # |
| C. | * |
| D. | ! |
| Answer» C. * | |
| 721. |
The master is also called as            in PCI terminology. |
| A. | initiator |
| B. | commander |
| C. | chief |
| D. | starter |
| Answer» B. commander | |
| 722. |
           provides a separate physical connection to the memory. |
| A. | pci bus |
| B. | pci interface |
| C. | pci bridge |
| D. | switch circuit |
| Answer» D. switch circuit | |
| 723. |
When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave. |
| A. | true |
| B. | false |
| Answer» C. | |
| 724. |
A complete transfer operation over the BUS, involving the address and a burst of data is called |
| A. | transaction |
| B. | transfer |
| C. | move |
| D. | procedure |
| Answer» B. transfer | |
| 725. |
              address space gives the PCI its plug and plays capability. |
| A. | configuration |
| B. | i/o |
| C. | memory |
| D. | all of the mentioned |
| Answer» B. i/o | |
| 726. |
The PCI BUS supports            address space/s. |
| A. | i/o |
| B. | memory |
| C. | configuration |
| D. | all of the mentioned |
| Answer» E. | |
| 727. |
PCI stands for |
| A. | peripheral component interconnect |
| B. | peripheral computer internet |
| C. | processor computer interconnect |
| D. | processor cable interconnect |
| Answer» B. peripheral computer internet | |
| 728. |
The               is the BUS used in Macintosh PC’s. |
| A. | nubus |
| B. | eisa |
| C. | pci |
| D. | none of the mentioned |
| Answer» B. eisa | |
| 729. |
The key feature of the PCI BUS is |
| A. | low cost connectivity |
| B. | plug and play capability |
| C. | expansion of bandwidth |
| D. | none of the mentioned |
| Answer» C. expansion of bandwidth | |
| 730. |
The PCI follows a set of standards primarily used in            PC’s. |
| A. | intel |
| B. | motorola |
| C. | ibm |
| D. | sun |
| Answer» D. sun | |
| 731. |
In a serial port interface, the INTR line is connected to |
| A. | status register |
| B. | shift register |
| C. | chip select |
| D. | none of the mentioned |
| Answer» B. shift register | |
| 732. |
The standard used in serial ports to facilitate communication is |
| A. | rs-246 |
| B. | rs-lnk |
| C. | rs-232-c |
| D. | both rs-246 and rs-lnk |
| Answer» D. both rs-246 and rs-lnk | |
| 733. |
The data transfer in UART is done in |
| A. | asynchronous start stop format |
| B. | synchronous start stop format |
| C. | isochronous format |
| D. | ebdic format |
| Answer» B. synchronous start stop format | |
| 734. |
The key feature of UART is |
| A. | its architectural design |
| B. | its simple implementation |
| C. | its general purpose usage |
| D. | its enhancement of connecting low speed devices |
| Answer» E. | |
| 735. |
UART stands for |
| A. | universal asynchronous relay transmission |
| B. | universal accumulator register transfer |
| C. | universal asynchronous receiver transmitter |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 736. |
The double buffer is used for |
| A. | enabling retrieval of multiple bits of input |
| B. | combining the input and output operations |
| C. | extending the buffer capacity |
| D. | none of the mentioned |
| Answer» B. combining the input and output operations | |
| 737. |
The serial port is used to connect basically            and processor. |
| A. | i/o devices |
| B. | speakers |
| C. | printer |
| D. | monitor |
| Answer» B. speakers | |
| 738. |
The transformation between the Parallel and serial ports is done with the help of |
| A. | flip flops |
| B. | logic circuits |
| C. | shift registers |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 739. |
In a general 8-bit parallel interface, the INTR line is connected to |
| A. | status and control unit |
| B. | ddr |
| C. | register select |
| D. | none of the mentioned |
| Answer» B. ddr | |
| 740. |
DDR stands for |
| A. | data direction register |
| B. | data decoding register |
| C. | data decoding rate |
| D. | none of the mentioned |
| Answer» B. data decoding register | |
| 741. |
In the output interface of the parallel port, along with the valid signal               is also sent. |
| A. | data |
| B. | idle signal |
| C. | interrupt |
| D. | acknowledge signal |
| Answer» C. interrupt | |
| 742. |
The mode of transmission of data, where one bit is sent for each clock cycle is |
| A. | asynchronous |
| B. | parallel |
| C. | serial |
| D. | isochronous |
| Answer» E. | |
| 743. |
The Status flag circuit is implemented using |
| A. | rs flip flop |
| B. | d flip flop |
| C. | jk flip flop |
| D. | xor circuit |
| Answer» C. jk flip flop | |
| 744. |
In a 32 bit processor, the A0 bit of the address line is connected to            of the parallel port interface. |
| A. | valid bit |
| B. | idle bit |
| C. | interrupt enable bit |
| D. | status or data register |
| Answer» E. | |
| 745. |
The disadvantage of using a parallel mode of communication is |
| A. | it is costly |
| B. | leads to erroneous data transfer |
| C. | security of data |
| D. | all of the mentioned |
| Answer» B. leads to erroneous data transfer | |
| 746. |
The output of the encoder circuit is/are |
| A. | ascii code |
| B. | ascii code and the valid signal |
| C. | encoded signal |
| D. | none of the mentioned |
| Answer» C. encoded signal | |
| 747. |
The best mode of connection between devices which need to send or receive large amounts of data over a short distance is |
| A. | bus |
| B. | serial port |
| C. | parallel port |
| D. | isochronous port |
| Answer» D. isochronous port | |
| 748. |
To overcome multiple signals being generated upon a single press of the button, we make use of |
| A. | generator circuit |
| B. | debouncing circuit |
| C. | multiplexer |
| D. | xor circuit |
| Answer» C. multiplexer | |
| 749. |
The            circuit enables the generation of the ASCII code when the key is pressed. |
| A. | generator |
| B. | debouncing |
| C. | encoder |
| D. | logger |
| Answer» D. logger | |
| 750. |
IDE stands for |
| A. | integrated device electronics |
| B. | international device encoding |
| C. | industrial decoder electronics |
| D. | international decoder encoder |
| Answer» B. international device encoding | |