American National Standard Interface

American National Standards Institute

American National Standard Interface

American Network Standard Interfacing

American Network Security Interrupt

The main virtue for using single Bus structure is

Cost effective connectivity and speed

Cost effective connectivity and ease of attaching peripheral devices

The copy-back protocol is used

To remove the contents of the cache and push it on to the memory

To copy the contents of the memory onto the cache

To update the contents of the memory from the cache

To remove the contents of the cache and push it on to the memory

The write-through procedure is used

To write onto the memory directly

To write and read from memory simultaneously

To write directly on the memory and the cache simultaneously

The spatial aspect of the locality of reference means

That the recently executed instruction is executed again next

That the recently executed wont be executed again

That the instruction executed will be executed at a later time

That the instruction in close proximity of the instruction executed will be executed in future

The temporal aspect of the locality of reference means

That the recently executed instruction wont be executed soon

That the recently executed instruction is temporarily not referenced

That the recently executed instruction will be executed soon again

The reason for the implementation of the cache memory is ___

To reduce the memory access and cycle time

To increase the internal memory of the system

The difference in speeds of operation of the processor and memory

To reduce the memory access and cycle time

The drawback of building a large memory with DRAM is ______

The inefficient memory organisation

The disadvantage of the EPROM chip is ____

The need to remove the chip physically to reprogram it

585 + Mcqs in Basic Operational Concept Page 5 McqOptions

201.	The general purpose registers are combined into a block called as _
A.	Register bank
B.	Register Case
C.	Register file
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

202.	ANSI stands for ___
A.	American National Standards Institute
B.	American National Standard Interface
C.	American Network Standard Interfacing
D.	American Network Security Interrupt
Answer» B. American National Standard Interface

Discussion

203.	The ISA standard Buses are used to connect __
A.	RAM and processor
B.	GPU and processor
C.	Harddisk and Processor
D.	CD/DVD drives and Processor
Answer» D. CD/DVD drives and Processor

Discussion

204.	________ signal enables the processor to wait for the memory operation to complete.
A.	MFC
B.	TLB
C.	WMFC
D.	ALB
Answer» D. ALB

Discussion

205.	The main virtue for using single Bus structure is
A.	Fast data transfers
B.	Cost effective connectivity and speed
C.	Cost effective connectivity and ease of attaching peripheral devices
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

206.	The small extremly fast, RAM’s all called as __
A.	Cache
B.	Heaps
C.	Accumulators
D.	Stacks
Answer» C. Accumulators

Discussion

207.	The completion of the memroy operation is indicated using ______ signal.
A.	MFC
B.	WMFC
C.	CFC
D.	None of the mentioned
Answer» B. WMFC

Discussion

208.	______ signal is used to show complete of memory operation.
A.	MFC
B.	WMFC
C.	CFC
D.	None of the mentioned
Answer» B. WMFC

Discussion

209.	The input and output of the registers are governed by ___
A.	Transistors
B.	Diodes
C.	Gates
D.	Switches
Answer» E.

Discussion

210.	When two or more clock cycles are used to complete data transfer it is called as _
A.	Single phase clocking
B.	Multi-phase clocking
C.	Multi-phase clocking
D.	None of the mentioned
Answer» C. Multi-phase clocking

Discussion

211.	The registers,ALU and the interconnecting path together are called as _
A.	Control path
B.	Flow path
C.	Data path
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

212.	Which register is connected to the MUX ?
A.	Y
B.	Z
C.	R0
D.	Temp
Answer» B. Z

Discussion

213.	The transparent register/s is/are ____
A.	Y
B.	Z
C.	Temp
D.	All of the mentioned
Answer» E.

Discussion

214.	The CPU is also called as _
A.	Processor hub
B.	ISP
C.	Controller
D.	All of the mentioned
Answer» C. Controller

Discussion

215.	Which register in the processor is single directional ?
A.	MAR
B.	MDR
C.	PC
D.	Temp
Answer» B. MDR

Discussion

216.	In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ___
A.	Hit
B.	Miss
C.	Delay
D.	None of the mentioned
Answer» B. Miss

Discussion

217.	The extra time needed to bring the data into memory in case of a miss is called as _
A.	Delay
B.	Propagation time
C.	Miss penalty
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

218.	The number failed attempts to access memory, stated in the form of fraction is called as ____
A.	Hit rate
B.	Miss rate
C.	Failure rate
D.	Delay rate
Answer» C. Failure rate

Discussion

219.	In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.
A.	Delay
B.	Miss
C.	Hit
D.	Delayed hit
Answer» C. Hit

Discussion

220.	The number successful accesses to memory stated as a fraction is called as __
A.	Hit rate
B.	Miss rate
C.	Success rate
D.	Access rate
Answer» B. Miss rate

Discussion

221.	The main memory is structured into modules each with its own address register called ____
A.	ABR
B.	TLB
C.	TLB
D.	IR
Answer» B. TLB

Discussion

222.	Data which is not up-to date is called as ____
A.	Spoilt data
B.	Stale data
C.	Dirty data
D.	None of the mentioned
Answer» C. Dirty data

Discussion

223.	The bit used to indicate whether the block was recently used or not is ______
A.	Idol bit
B.	Control bit
C.	Refernece bit
D.	Dirty bit
Answer» E.

Discussion

224.	A control bit called ____ has to be provided to each blocj in set-associative.
A.	Idol bit
B.	Valid bit
C.	Reference bit
D.	All of the mentioned
Answer» C. Reference bit

Discussion

225.	In set-associative technique, the blocks are grouped into ______ sets.
A.	4
B.	8
C.	12
D.	6
Answer» E.

Discussion

226.	The method of mapping the consecutive memory blocks to consecutive cache blocks is called __
A.	Set associative
B.	Associative
C.	Direct
D.	Indirect
Answer» D. Indirect

Discussion

227.	The technique of searching for a block by going through all the tags is __
A.	Linear search
B.	Binary search
C.	Associative search
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

228.	In associative mapping, in a 16 bit system the tag field has ______ bits.
A.	12
B.	8
C.	9
D.	10
Answer» B. 8

Discussion

229.	While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ____
A.	Tag
B.	Block
C.	Word
D.	Id
Answer» B. Block

Discussion

230.	The approach where the memory contents are transfered directly to the processor from the memory is called _
A.	Read-later
B.	Read-through
C.	Early-start
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

231.	The only draw back of using the early start protocol is _____
A.	Time delay
B.	Complexity of circuit
C.	Latency
D.	High miss rate
Answer» C. Latency

Discussion

232.	In ________ protocol the information is directly written into main memory.
A.	Write through
B.	Write back
C.	Write first
D.	None of the mentioned
Answer» B. Write back

Discussion

233.	The memory blocks are mapped on to the cache with the help of ___
A.	Hash functions
B.	Vectors
C.	Mapping functions
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

234.	The copy-back protocol is used
A.	To copy the contents of the memory onto the cache
B.	To update the contents of the memory from the cache
C.	To remove the contents of the cache and push it on to the memory
D.	None of the mentioned
Answer» C. To remove the contents of the cache and push it on to the memory

Discussion

235.	The write-through procedure is used
A.	To write onto the memory directly
B.	To write and read from memory simultaneously
C.	To write directly on the memory and the cache simultaneously
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

236.	The bit used to signify that the cache location is updated is __
A.	Dirty bit
B.	Update bit
C.	Reference bit
D.	Flag bit
Answer» B. Update bit

Discussion

237.	The spatial aspect of the locality of reference means
A.	That the recently executed instruction is executed again next
B.	That the recently executed wont be executed again
C.	That the instruction executed will be executed at a later time
D.	That the instruction in close proximity of the instruction executed will be executed in future
Answer» E.

Discussion

238.	The correspondence between the main memory blocks and those in the cache is given by _____
A.	Hash function
B.	Mapping function
C.	Locale function
D.	Assign function
Answer» C. Locale function

Discussion

239.	The algorithm to remove and place new contents into the cache is called ___
A.	Replacement algorithm
B.	Renewal algorithm
C.	Updation
D.	None of the mentioned
Answer» B. Renewal algorithm

Discussion

240.	The temporal aspect of the locality of reference means
A.	That the recently executed instruction wont be executed soon
B.	That the recently executed instruction is temporarily not referenced
C.	That the recently executed instruction will be executed soon again
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

241.	The effectiveness of the cache memory is based on the property of _
A.	Locality of reference
B.	Memory localisation
C.	Memory size
D.	None of the mentioned
Answer» B. Memory localisation

Discussion

242.	The reason for the implementation of the cache memory is ___
A.	To increase the internal memory of the system
B.	The difference in speeds of operation of the processor and memory
C.	To reduce the memory access and cycle time
D.	All of the mentioned
Answer» C. To reduce the memory access and cycle time

Discussion

243.	The next level of memory hierarchy after the L2 cache is __
A.	Secondary storage
B.	TLB
C.	Main memory
D.	Register
Answer» E.

Discussion

244.	The last on the hierarchy scale of memory devices is __
A.	Main memory
B.	Secondary memory
C.	TLB
D.	Flash drives
Answer» C. TLB

Discussion

245.	The larger memory placed between the primary cache and the memory is called __
A.	Level 1 cache
B.	Level 2 cache
C.	EEPROM
D.	TLB
Answer» C. EEPROM

Discussion

246.	The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called __
A.	Level 1 cache
B.	Level 2 cache
C.	Registers
D.	TLB
Answer» B. Level 2 cache

Discussion

247.	The fastest data access is provided using _
A.	Caches
B.	DRAM’s
C.	SRAM’s
D.	Registers
Answer» E.

Discussion

248.	The flash memory modules designed to replace the functioning of an harddisk is _
A.	RIMM
B.	Flash drives
C.	FIMM
D.	DIMM
Answer» C. FIMM

Discussion

249.	The drawback of building a large memory with DRAM is ______
A.	The large cost factor
B.	The inefficient memory organisation
C.	The Slow speed of operation
D.	All of the mentioned
Answer» D. All of the mentioned

Discussion

250.	The disadvantage of the EPROM chip is ____
A.	The high cost factor
B.	The low efficiency
C.	The low speed of operation
D.	The need to remove the chip physically to reprogram it
Answer» E.

Discussion

Explore topic-wise MCQs in Computer Organization.

The general purpose registers are combined into a block called as _

ANSI stands for ___

The ISA standard Buses are used to connect __

________ signal enables the processor to wait for the memory operation to complete.

The main virtue for using single Bus structure is

The small extremly fast, RAM’s all called as __

The completion of the memroy operation is indicated using ______ signal.

______ signal is used to show complete of memory operation.

The input and output of the registers are governed by ___

When two or more clock cycles are used to complete data transfer it is called as _

The registers,ALU and the interconnecting path together are called as _

Which register is connected to the MUX ?

The transparent register/s is/are ____

The CPU is also called as _

Which register in the processor is single directional ?

In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ___

The extra time needed to bring the data into memory in case of a miss is called as _

The number failed attempts to access memory, stated in the form of fraction is called as ____

In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.

The number successful accesses to memory stated as a fraction is called as __

The main memory is structured into modules each with its own address register called ____

Data which is not up-to date is called as ____

The bit used to indicate whether the block was recently used or not is ______

A control bit called ____ has to be provided to each blocj in set-associative.

In set-associative technique, the blocks are grouped into ______ sets.

The method of mapping the consecutive memory blocks to consecutive cache blocks is called __

The technique of searching for a block by going through all the tags is __

In associative mapping, in a 16 bit system the tag field has ______ bits.

While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ____

The approach where the memory contents are transfered directly to the processor from the memory is called _

The only draw back of using the early start protocol is _____

In ________ protocol the information is directly written into main memory.

The memory blocks are mapped on to the cache with the help of ___

The copy-back protocol is used

The write-through procedure is used

The bit used to signify that the cache location is updated is __

The spatial aspect of the locality of reference means

The correspondence between the main memory blocks and those in the cache is given by _____

The algorithm to remove and place new contents into the cache is called ___

The temporal aspect of the locality of reference means

The effectiveness of the cache memory is based on the property of _

The reason for the implementation of the cache memory is ___

The next level of memory hierarchy after the L2 cache is __

The last on the hierarchy scale of memory devices is __

The larger memory placed between the primary cache and the memory is called __

The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called __

The fastest data access is provided using _

The flash memory modules designed to replace the functioning of an harddisk is _

The drawback of building a large memory with DRAM is ______

The disadvantage of the EPROM chip is ____