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This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
151. |
The drawback of Manchester encoding is __ |
A. | The cost of the encoding scheme |
B. | The speed of encoding the data |
C. | The Latency offered |
D. | The low bit storage density provided |
Answer» E. | |
152. |
On of the most widely used schemes of encoding used is __ |
A. | NRZ-polar |
B. | RZ-polar |
C. | Manchester |
D. | Block encoding |
Answer» D. Block encoding | |
153. |
The virtual memory basically stores the next segment of data to be executed on the _________ |
A. | Secondary storage |
B. | Disks |
C. | RAM |
D. | ROM |
Answer» B. Disks | |
154. |
The main reason for the discontinuation of semi conductor based storage devices for providing large storage space is _ |
A. | Lack of sufficient resources |
B. | High cost per bit value |
C. | Lack of speed of operation |
D. | None of the mentioned |
Answer» C. Lack of speed of operation | |
155. |
For the synchronization of the read head, we make use of a __ |
A. | Framing bit |
B. | Synchronization bit |
C. | Clock |
D. | Dirty bit |
Answer» D. Dirty bit | |
156. |
The digital information is stored on the hard disk by __ |
A. | Applying a suitable electric pulse |
B. | Applying a suitable magnetic field |
C. | Applying a suitable nuclear field |
D. | By using optic waves |
Answer» B. Applying a suitable magnetic field | |
157. |
The asscociatively mapped virtual memory makes use of ___ |
A. | TLB |
B. | Page table |
C. | Frame table |
D. | None of the mentioned |
Answer» B. Page table | |
158. |
_____ translates logical address into physical address. |
A. | MMU |
B. | Translator |
C. | Compiler |
D. | Linker |
Answer» B. Translator | |
159. |
The main aim of virtual memory organisation is |
A. | To provide effective memory access |
B. | To provide better memory transfer |
C. | To improve the execution of the program |
D. | All of the mentioned |
Answer» E. | |
160. |
_________is used to implement virtual memory organisation. |
A. | Page table |
B. | Frame table |
C. | MMU |
D. | None of the mentioned |
Answer» D. None of the mentioned | |
161. |
The binary address issued to data or instructions are called as __ |
A. | Physical address |
B. | Location |
C. | Relocatable address |
D. | Logical address |
Answer» E. | |
162. |
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps.For the execution of the same instruction which processor is faster |
A. | A |
B. | B |
C. | Both take the same time |
D. | Insufficient information |
Answer» B. B | |
163. |
The techniques which move the program blocks to or from the physical memory is called as _ |
A. | Paging |
B. | Virtual memory organisation |
C. | Overlays |
D. | Framing |
Answer» C. Overlays | |
164. |
If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation) |
A. | 3 |
B. | ~2 |
C. | ~1 |
D. | 6 |
Answer» D. 6 | |
165. |
The program is divided into operable parts called as ___ |
A. | Frames |
B. | Segments |
C. | Pages |
D. | Sheets |
Answer» C. Pages | |
166. |
An effective to introduce parallelism in memory access is by _ |
A. | Memory interleaving |
B. | TLB |
C. | Pages |
D. | Frames |
Answer» B. TLB | |
167. |
The main purpose of having memory hierarchy is to |
A. | Reduce access time |
B. | Provide large capacity |
C. | Reduce propagation time |
D. | Reduce access time & Provide large capacity |
Answer» E. | |
168. |
The performance depends on |
A. | The speed of execution only |
B. | The speed of fetch and execution |
C. | The speed of fetch only |
D. | The hardware of the system only |
Answer» C. The speed of fetch only | |
169. |
A common measure of performance is |
A. | Price/performance ratio |
B. | Performance/price ratio |
C. | Operation/price ratio |
D. | None of the mentioned |
Answer» B. Performance/price ratio | |
170. |
The main objective of the computer system is |
A. | To provide optimal power operation |
B. | To provide best performance at low cost |
C. | To provide speedy operation at low power consumption |
D. | All of the mentioned |
Answer» C. To provide speedy operation at low power consumption | |
171. |
The key factor/s in commercial success of a computer is/are ___ |
A. | Performance |
B. | Cost |
C. | Speed |
D. | Both Performance and Cost |
Answer» E. | |
172. |
The counter that keeps track of how many times a block is most likely used is __ |
A. | Count |
B. | Reference counter |
C. | Use counter |
D. | Probable counter |
Answer» C. Use counter | |
173. |
In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ___ |
A. | Hit |
B. | Miss |
C. | Delay |
D. | None of the mentioned |
Answer» B. Miss | |
174. |
The LRU provides very bad performance when it comes to _____ |
A. | Blocks being accessed is sequential |
B. | When the blocks are ramdomised |
C. | When the consecutive blocks accessed are in the extremes |
D. | None of the mentioned |
Answer» B. When the blocks are ramdomised | |
175. |
The algorithm which removes the recently used page first is __ |
A. | LRU |
B. | MRU |
C. | OFM |
D. | None of the mentioned |
Answer» C. OFM | |
176. |
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs. |
A. | Delay |
B. | Miss |
C. | Hit |
D. | Delayed hit |
Answer» C. Hit | |
177. |
THe algorithm which replaces the block which has not been referenced for awhile is called _____ |
A. | LRU |
B. | ORF |
C. | Direct |
D. | Both LRU and ORF |
Answer» B. ORF | |
178. |
The surroundings of the recently accessed block is called as ___ |
A. | Neighbourhood |
B. | Neighbour |
C. | Locality of reference |
D. | None of the mentioned |
Answer» D. None of the mentioned | |
179. |
Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is _____ |
A. | Horizontal organisation |
B. | Vertical organisation |
C. | Diagonal organisation |
D. | None of the mentioned |
Answer» C. Diagonal organisation | |
180. |
The case/s where micro-programmed can perform well |
A. | When it requires to check the condition codes |
B. | When it has to choose between the two alternatives |
C. | When it is triggered by an interrupt |
D. | None of the mentioned |
Answer» E. | |
181. |
Every time a new instruction is loaded into IR the output of ________ is loaded into UPC |
A. | Starting address generator |
B. | Loader |
C. | Linker |
D. | Clock |
Answer» B. Loader | |
182. |
To read the control words sequentially _________ is used. |
A. | PC |
B. | IR |
C. | UPC |
D. | None of the mentioned |
Answer» D. None of the mentioned | |
183. |
The special memory used to store the micro routines of a computer is _ |
A. | Control table |
B. | Control store |
C. | Control mart |
D. | Control shop |
Answer» C. Control mart | |
184. |
Individual control words of the micro routine are called as __ |
A. | Micro task |
B. | Micro operation |
C. | Micro instruction |
D. | Micro command |
Answer» D. Micro command | |
185. |
A sequence of control words corresponding to a control sequence is called ___ |
A. | Micro routine |
B. | Micro function |
C. | Micro procedure |
D. | None of the mentioned |
Answer» B. Micro function | |
186. |
A word whose individual bits represent a control signal is __ |
A. | Command word |
B. | Control word |
C. | Co-ordination word |
D. | Generation word |
Answer» C. Co-ordination word | |
187. |
In micro-programmed approach, the signals are generated by __ |
A. | Machine instructions |
B. | System programs |
C. | Utility tools |
D. | None of the mentioned |
Answer» B. System programs | |
188. |
The disadvantage/s of the hardwired approach is |
A. | It is less flexible |
B. | It cannot be used for complex instructions |
C. | It is costly |
D. | less flexible & cannot be used for complex instructions |
Answer» E. | |
189. |
What does the RUN signal do ? |
A. | It causes the termination of a signal |
B. | It causes a particular signal to perform its operation |
C. | It causes a particular signal to end |
D. | It increments the step counter by one |
Answer» E. | |
190. |
The benefit of using this approach is |
A. | It is cost effective |
B. | It is highly efficient |
C. | It is very reliable |
D. | It increases the speed of operation |
Answer» E. | |
191. |
What does the end instruction do ? |
A. | It ends the generation of a signal |
B. | It ends the complete generation process |
C. | It starts a new instruction fetch cycle and resets the counter |
D. | It is used to shift the control to the processor |
Answer» D. It is used to shift the control to the processor | |
192. |
What does the hardwired control generator consist of ? |
A. | Decoder/encoder |
B. | Condition codes |
C. | Control step counter |
D. | All of the mentioned |
Answer» E. | |
193. |
______ are the different type/s of generating control signals. |
A. | Micro-programmed |
B. | Hardwired |
C. | Micro-instruction |
D. | Both Micro-programmed and Hardwired |
Answer» E. | |
194. |
The type of control signal are generated based on, |
A. | contents of the step counter |
B. | Contents of IR |
C. | Contents of condition flags |
D. | All of the mentioned |
Answer» E. | |
195. |
In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU. |
A. | MUX |
B. | DE-MUX |
C. | En-CDS |
D. | None of the mentioned |
Answer» B. DE-MUX | |
196. |
CISC stands for ____ |
A. | Complete Instruction Sequential Compilation |
B. | Computer Integrated Sequential Compiler |
C. | Complex Instruction Set Computer |
D. | Complex Instruction Sequential Compilation |
Answer» D. Complex Instruction Sequential Compilation | |
197. |
If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation) |
A. | 3 |
B. | ~2 |
C. | ~1 |
D. | 6 |
Answer» D. 6 | |
198. |
The main advantage of multiple bus organisation over single bus is ___ |
A. | Reduction in the number of cycles for execution |
B. | Increase in size of the registers |
C. | Better Connectivity |
D. | None of the mentioned |
Answer» B. Increase in size of the registers | |
199. |
In a three BUS architecture, how many input and output ports are there ? |
A. | 2 output and 2 input |
B. | 1 output and 2 input |
C. | 2 output and 1 input |
D. | 1 output and 1 input |
Answer» D. 1 output and 1 input | |
200. |
IBM developed a bus standard for their line of computers ‘PC AT’ called |
A. | IB bus |
B. | M-bus |
C. | ISA |
D. | None of the mentioned |
Answer» D. None of the mentioned | |