MCQOPTIONS
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MCQOPTIONS
This section includes 209 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessor knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
n-channel MOS devices are preferred over p-channel MOS devices for digital circuit because |
| A. | lower power dissipation |
| B. | higher power dissipation |
| C. | higher mobility of electrons than holes |
| D. | None of these |
| Answer» D. None of these | |
| 52. |
The propagation delay time of a non-saturated bipolar logic family |
| A. | is less than that of a saturated bipolar logic family |
| B. | is same as that of a saturated bipolar logic family |
| C. | is more than that of a saturated bipolar logic family |
| D. | None of these |
| Answer» B. is same as that of a saturated bipolar logic family | |
| 53. |
n-p-n transistors are preferred over p-n-p transistors for digital circuit families because |
| A. | they require positive supply voltage |
| B. | they consume less power |
| C. | of the requirements of positive logic system |
| D. | the mobility of electrons is higher than the mobility of holes |
| Answer» E. | |
| 54. |
The 2 s complement representation in 8 bit format is 11010000. The equivalent hexadecimal representation is |
| A. | 50 |
| B. | D0 |
| C. | 30 |
| D. | 30 |
| Answer» D. 30 | |
| 55. |
Which of following gates is shown as coincidence detector? |
| A. | AND gate |
| B. | OR gate |
| C. | NOT gate |
| D. | NAND gate |
| Answer» B. OR gate | |
| 56. |
Given two numbers A and B in sign magnitude representation in an eight bit format A = 00011110 and B = 10011100, the corresponding decimal numbers respectively are |
| A. | 30 and 156 |
| B. | 14 and 12 |
| C. | 30 and 100 |
| D. | 28 and 30 |
| Answer» D. 28 and 30 | |
| 57. |
For fastest switching operation, it is preferred to use |
| A. | Normal p-n junction diode |
| B. | Schottky diodes |
| C. | Vacuum diodes |
| D. | Zener diodes |
| Answer» C. Vacuum diodes | |
| 58. |
For large scale integration, the following logic gate family is preferred |
| A. | MOS |
| B. | TTL |
| C. | ECL |
| D. | RTL |
| Answer» B. TTL | |
| 59. |
In the above question the representation for (N 1) is |
| A. | 1010 |
| B. | 1100 |
| C. | 1110 |
| D. | none of these |
| Answer» C. 1110 | |
| 60. |
Find (177) |
| A. | 128 |
| B. | 200 |
| C. | 178 |
| D. | 179 |
| Answer» B. 200 | |
| 61. |
The power consumption is more for the following logic gate family |
| A. | ECL |
| B. | TTL |
| C. | CMOS |
| D. | DCTL |
| Answer» B. TTL | |
| 62. |
The negative decimal number N in 2 s complement representation is 1011. Then the representation for (N + 1) is |
| A. | 1010 |
| B. | 1100 |
| C. | 1110 |
| D. | none of these |
| Answer» B. 1100 | |
| 63. |
According to De Morgan s second theorem |
| A. | A NAND gate is always complimentary to an AND gate |
| B. | An AND gate is equivalent to a bubbled NAND gate |
| C. | A NAND gate is equivalent to a bubbled AND gate |
| D. | A NAND gate is equivalent to a bubbled OR gate |
| Answer» E. | |
| 64. |
In 2 S complement adder-subtractor, given the numbers X = 00011000 and Y = 11110000. They stand respectively for |
| A. | 24 and 240 |
| B. | 18 and 15 |
| C. | 6 and 15 |
| D. | 24 and 16 |
| Answer» E. | |
| 65. |
NAND-NAND circuits are equivalent to |
| A. | AND-OR circuits |
| B. | OR-XOR circuits |
| C. | OR-NOT circuits |
| D. | All of these |
| Answer» B. OR-XOR circuits | |
| 66. |
The logic gate family which consumes less power is |
| A. | ECL |
| B. | TTL |
| C. | IIL |
| D. | CMOS |
| Answer» E. | |
| 67. |
The output of a gate is 1 if and only if all the inputs of that gate are high, what is that gate? |
| A. | NOT |
| B. | NAND |
| C. | NOR |
| D. | AND |
| Answer» E. | |
| 68. |
Tri-state logic is used for |
| A. | improving the figure of merit |
| B. | increasing the fan-out |
| C. | bus oriented systems |
| D. | improving the speed of operation |
| Answer» D. improving the speed of operation | |
| 69. |
The output of a gate is 1 only for number of high inputs, what is that gate? |
| A. | X-NOR |
| B. | X-OR |
| C. | NAND |
| D. | NOR |
| Answer» C. NAND | |
| 70. |
Wired logic is not possible in |
| A. | ECL |
| B. | TTL with active pull-up |
| C. | open-collector TTL |
| D. | TTL with passive pull-up |
| Answer» C. open-collector TTL | |
| 71. |
Identify the universal gate from the following gates |
| A. | OR gate |
| B. | AND gate |
| C. | X-OR |
| D. | NAND |
| Answer» E. | |
| 72. |
Complementary outputs are available in |
| A. | ECL gates |
| B. | TTL gates |
| C. | DTL gates |
| D. | RTL gates |
| Answer» B. TTL gates | |
| 73. |
The output of a gate is zero if and only if when all the inputs are high. What is that gate? |
| A. | AND gate |
| B. | OR gate |
| C. | NAND gate |
| D. | NOR gate |
| Answer» D. NOR gate | |
| 74. |
The minimum number of NAND gates required to realize EX-OR gate are |
| A. | 5 |
| B. | 4 |
| C. | 3 |
| D. | 6 |
| Answer» C. 3 | |
| 75. |
The open input terminal of a TTL gate |
| A. | will assume a very high voltage |
| B. | will behave as if it is connected to logic 0 level |
| C. | will behave as if it is connected to logic 1 level |
| D. | none of these |
| Answer» D. none of these | |
| 76. |
There are four Boolean variables x |
| A. | m (3, 12, 13) |
| B. | m (3, 6) |
| C. | m (3, 12) |
| D. | 0 |
| Answer» B. m (3, 6) | |
| 77. |
The output of a gate Y = AB + A B , where A and B are inputs, what is that gate? |
| A. | EX-NOR |
| B. | NAND |
| C. | EX-OR |
| D. | All of these |
| Answer» B. NAND | |
| 78. |
The figure of merit of a logic gate family is given by |
| A. | gain bandwidth |
| B. | propagation delay power dissipation |
| C. | fan-out propagation delay time |
| D. | noise margin power dissipation |
| Answer» C. fan-out propagation delay time | |
| 79. |
HTL is the modified version of logic gate family. |
| A. | DCTL |
| B. | TTL |
| C. | CMOS |
| D. | ECL |
| Answer» C. CMOS | |
| 80. |
HTL is preferred in the industrial environment because of |
| A. | low power dissipation |
| B. | high speed |
| C. | low noise margin |
| D. | highest noise margin |
| Answer» E. | |
| 81. |
A switching function |
| A. | m (1, 3, 5, 7, 9) |
| B. | m (3, 5, 7, 9, 11) |
| C. | m (3, 5, 9, 11, 13) |
| D. | m (5, 7, 9, 11, 13) |
| Answer» C. m (3, 5, 9, 11, 13) | |
| 82. |
The switching function f (A, B, C, D) = m (5, 9, 11, 14) can written as |
| A. | A B C D + A B C D + AB CD + ABCD |
| B. | A B C D + AB C D + A B CD + ABCD |
| C. | A BC D + A BC D + AB C D + ABCD |
| D. | None of these |
| Answer» B. A B C D + AB C D + A B CD + ABCD | |
| 83. |
In an 8085 microprocessor based system, the contents of SP are 1000H. PUSH B instruction will transfer the contents of registers B and C respectively for memory locations |
| A. | 0FFF H and 0FFE H |
| B. | 0FFE H and 0FFF H |
| C. | 1000 H and 0FFF H |
| D. | 1000 H and 1001 H |
| Answer» B. 0FFE H and 0FFF H | |
| 84. |
The output 0 and 1 level for TTL logic family is approximately |
| A. | 0.1 and 5 V |
| B. | 0.6 and 3.5 V |
| C. | 0.9 and 1.75 V |
| D. | 1.75 and 0.9 V |
| Answer» C. 0.9 and 1.75 V | |
| 85. |
The switching function |
| A. | m (2, 3, 6) |
| B. | m (0, 1, 4, 5, 7) |
| C. | m (1, 2, 5, 6, 7) |
| D. | m (0, 2, 4, 6) |
| Answer» C. m (1, 2, 5, 6, 7) | |
| 86. |
In an 8085 microprocessor based system, the contents of SP are 2000H. POPH instruction will transfer the contents of memory location |
| A. | 2001H and 2002H to H and L registers respectively |
| B. | 2001 H and 2000H to H and L registers respectively |
| C. | 2000H and 1FFFH to H and L registers respectively |
| D. | 2000H and 1999H to H and L registers respectively |
| Answer» C. 2000H and 1FFFH to H and L registers respectively | |
| 87. |
The other canonical form of |
| A. | M (2, 3, 4, 6) |
| B. | M (2, 4, 6, 8) |
| C. | M (2, 5, 6, 7) |
| D. | M (1, 3, 5, 7) |
| Answer» B. M (2, 4, 6, 8) | |
| 88. |
An Intel 8085 processor is executing the program given below. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 89. |
The maximum frequency at which digital data can be applied to gate is defined as |
| A. | operating speed |
| B. | propagation speed |
| C. | binary level transition period |
| D. | charging time |
| Answer» B. propagation speed | |
| 90. |
MOS logic gate have no current hogging problem because the gate terminals are |
| A. | low input impedance |
| B. | zero impedance |
| C. | high impedance |
| D. | compensating effect |
| Answer» D. compensating effect | |
| 91. |
The switching speed of ECL is very high because |
| A. | it uses positive logic |
| B. | it uses negative logic |
| C. | it uses high speed transistors |
| D. | its transistors remain unsaturated |
| Answer» E. | |
| 92. |
If a three variable switching function is expressed as the product of maxterms by |
| A. | m (0, 3, 5, 6) |
| B. | M (1, 2, 4, 7) |
| C. | m (1, 2, 4, 7) |
| D. | M (1, 3, 4, 7) |
| Answer» D. M (1, 3, 4, 7) | |
| 93. |
The allowable supply voltage range for TTL logic gate family is |
| A. | 2 to 5.6 V |
| B. | 3.5 to 6.2 V |
| C. | 4.75 V to 5.25 V |
| D. | 4 to 6 V |
| Answer» D. 4 to 6 V | |
| 94. |
A function with don t care is as follows. g (X, Y, Z) = m (5, 6) + dc (1, 2, 4) For above function consider following expression |
| A. | 1, 2 and 3 |
| B. | 1, 2 and 4 |
| C. | 1 and 4 |
| D. | 1 and 3 |
| Answer» C. 1 and 4 | |
| 95. |
The dual of Boolean theorem x (y + z) = xy + xz is |
| A. | x + yz = xy + xz |
| B. | x (y + z) = (x + y) (x + z) |
| C. | x + yz = (x + y) (x + z) |
| D. | None of these |
| Answer» D. None of these | |
| 96. |
Identify which is not a saturated logic gate family from the following? |
| A. | TTL |
| B. | DTL |
| C. | HTL |
| D. | ECL |
| Answer» E. | |
| 97. |
Given Boolean theorem AB + A C + BC = AB + A C which of the following is true? |
| A. | (A + B) (A + C) (B + C) = (A + B) (A + C) |
| B. | AB + A C + BC = AB + BC |
| C. | AB + A C + BC = (A + B) (A + C) (B + C) |
| D. | (A + B) (A + C) (B + C) = AB + A C |
| Answer» B. AB + A C + BC = AB + BC | |
| 98. |
Identify the logic gate family which consumes maximum power and which has minimum propagation delay |
| A. | MOS |
| B. | TTL |
| C. | ECL |
| D. | CMOS |
| Answer» D. CMOS | |
| 99. |
Choose the correct statements from the following |
| A. | PROM contains a programmable AND array and a fixed OR array |
| B. | PLA contains a fixed AND array and a programmable OR array |
| C. | PROM contains a fixed AND array and a programmable OR array |
| D. | PLA contains a programmable AND array and a programmable OR array |
| E. | Both C and D |
| Answer» F. | |
| 100. |
Identify the logic gate family which consumes less power and which has maximum fan-out |
| A. | MOS |
| B. | TTL |
| C. | ECL |
| D. | CMOS |
| Answer» E. | |