When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:

When both nMOS and pMOS transistors of CMOS logic design are in OFF c

1.	When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:
A.	1 or Vdd or HIGH state
B.	0 or ground or LOW state
C.	High impedance or floating(Z)
D.	None of the mentioned
Answer» D. None of the mentioned