MCQOPTIONS
Bookmark
Saved Bookmarks
→
Vlsi
→
Characteristics Npn Bipolar Transistors in Vlsi
→
For a pseudo nMOS design the impedance of pull up..
1.
For a pseudo nMOS design the impedance of pull up and pull down ratio is
A.
4:1
B.
1:4
C.
3:1
D.
1:3
Answer» D. 1:3
Show Answer
Discussion
No Comment Found
Post Comment
Related MCQs
For a pseudo nMOS design the impedance of pull up and pull down ratio is
BiCMOS is used for ____ fan-out.
The CMOS inverter has _____ power dissipation.
FOR_A_PSEUDO_NMOS_DESIGN_THE_IMPEDANCE_OF_PULL_UP_AND_PULL_DOWN_RATIO_IS?$
Which gate is faster?
Which can handle high capacitance load?
BiCMOS is used for ____ fan-out
In CMOS NAND gate, p transistors are connected in
NAND gate delay can be given as
As the number of inputs increases, the NAND gate delay
Reply to Comment
×
Name
*
Email
*
Comment
*
Submit Reply