Assertion (A): In a parallel in-serial out shift register data is loaded one bit-at a time.Reason (R): A serial in-serial out shift register can be used to introduce a time delay.

• A. Both A and R are correct and R is correct explanation of A
• B. Both A and R are correct but R is not correct explanation of A
• C. A is true, R is false
• D. A is false, R is true