A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as _______

A user has designed JK flip flop by using the VHDL code. The output is

1.	A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as _______
A.	Switching condition
B.	Master slave condition
C.	Race around condition
D.	Edge triggered condition
Answer» D. Edge triggered condition