Explore topic-wise MCQs in Vhdl.

This section includes 7 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.

1.

Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?#

A. By using IF(clk = ‘1’)
B. By using ‘EVENT keyword
C. By using a CASE statement
D. By using a LOOP
Answer» B. By using ‚Äö√Ñ√∂‚àö√ë‚àö‚â§EVENT keyword
Discussion
2.

A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?

A. By using WAIT FOR statement
B. By using AFTER clause
C. By using a separate process
D. By using WAIT ON statement
Answer» C. By using a separate process
Discussion
3.

WAIT FOR statement is useful only for _________

A. Synthesis
B. Simulation
C. Gate level implementation
D. Optimization
Answer» D. Optimization
Discussion
4.

D flip flop

A. Inverter
B. OR gate
C. Shift register
Answer» C. Shift register
Discussion
5.

In a procedure, __________ statement is not supported.

A. WAIT UNTIL
B. WAIT ON
C. WAIT FOR
D. WAIT FOR and unconditional WAIT
Answer» E.
Discussion
6.

Which of the following is true about WAIT ON statement?

A. WAIT ON statement is supported by synthesis tools
B. WAIT ON statement is not supported by synthesis tools
C. WAIT ON statement is supported in a clocked process only
D. WAIT ON statement is supported in a combinational process
Answer» E.
Discussion
7.

Which of the following is true about WAIT UNTIL statement?

A. WAIT UNTIL statement is supported by synthesis tools
B. WAIT UNTIL statement is not supported by synthesis tools
C. WAIT UNTIL statement is supported in a clocked process only
D. WAIT UNTIL statement is supported in a combinational process
Answer» D. WAIT UNTIL statement is supported in a combinational process
Discussion