MCQOPTIONS
Bookmark
Saved Bookmarks
→
Vhdl
→
User Defined Data Types in Vhdl
→
D flip flop..
1.
D flip flop
A.
Inverter
B.
OR gate
C.
Shift register
Answer» C. Shift register
Show Answer
Discussion
No Comment Found
Post Comment
Related MCQs
Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?#
A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?
WAIT FOR statement is useful only for _________
D flip flop
In a procedure, __________ statement is not supported.
Which of the following is true about WAIT ON statement?
Which of the following is true about WAIT UNTIL statement?
Reply to Comment
×
Name
*
Email
*
Comment
*
Submit Reply