Explore topic-wise MCQs in Vhdl.

This section includes 12 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.

1.

The condition to implement the simulation delta delay is _______

A. All events must be synchronous
B. The events must have at least one sequential circuit
C. No condition
D. All events must be zero delay event
Answer» E.
Discussion
2.

Which of the following is not the application of inertial delay?

A. Buffer delay
B. PC wire line delay
C. Simple delay in OR gate
D. Inverter delay
Answer» C. Simple delay in OR gate
Discussion
3.

Which of the following delay model follows the principle of preemption?

A. Inertial delay
B. Transport delay
C. Delta delay
D. Wire delay
Answer» B. Transport delay
Discussion
4.

For zero delay events, which of the following mechanism is used?

A. Transport delay mechanism
B. Inertial delay mechanism
C. Delta delay mechanism
D. Preemption delay mechanism
Answer» D. Preemption delay mechanism
Discussion
5.

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?

A. 20 ns
B. 30 ns
C. 40 ns
D. Output will remain zero
Answer» C. 40 ns
Discussion
6.

The keyword TRANSPORT in any assignment statement specifies _______

A. Transport delay
B. Transfer the right operand immediately to left operand
C. Transporting the value of left operand to right operand
D. Inertial delay
Answer» B. Transfer the right operand immediately to left operand
Discussion
7.

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?

A. 30 ns
B. 40 ns
C. 20 ns
D. Output will remain zero
Answer» E.
Discussion
8.

In inertial delay, if the signal value is maintained for the time period less than delay tiem, then the signal value does not change.

A. True
B. False
Answer» B. False
Discussion
9.

Transport delay is a kind of __________

A. Synthesis delay
B. Simulation delay
C. Inertial delay
D. Wire delay
Answer» E.
Discussion
10.

The inertia value in inertial delay model is equal to _________

A. Initial value
B. Delay
C. Input value at a specific time
D. Output value at a specific time
Answer» C. Input value at a specific time
Discussion
11.

What must be overcome by the output signal to change the value in case of inertial delay?

A. Time
B. Error
C. Inertia
D. Pulse
Answer» D. Pulse
Discussion
12.

Which of the following is default delay in VHDL?

A. Inertial delay
B. Transport delay
C. Delta delay
D. Wire delay
Answer» B. Transport delay
Discussion