The flexibility of the GAL16V8 is in its ________.

programmable output logic macro cells

A macrocell is ________.

a type of one-time programmable SPLD

an example of intellectual property

In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

asynchronous preset, synchronous reset

asynchronous reset, synchronous preset

asynchronous preset, synchronous reset

asynchronous clear, synchronous set

asynchronous set, synchronous clear

157 + Mcqs in Programmable Logic Device in Digital Electronics Page 1 McqOptions

1.	The EPM 7128S is a(n) ________ device.
A.	PLD
B.	JTAG
C.	EEPROM
D.	ISP
Answer» E.

Discussion

2.	The GAL16V8 has eight dedicated input pins.
A.	1
B.
Answer» B.

Discussion

3.	Gate arrays are ULSI circuits that offer hundreds of thousands of gates.
A.	1
B.
Answer» B.

Discussion

4.	The hard core portions of FPGAs are reprogrammable in the field.
A.	1
B.
Answer» C.

Discussion

5.	FLEX10K devices are generally classified as ________.
A.	PLDs
B.	FPGAs
C.	HCPLDs
D.	CPLDs
Answer» C. HCPLDs

Discussion

6.	The GAL22V10 has 12 outputs pins and 10 input pins.
A.	1
B.
Answer» C.

Discussion

7.	Design costs for standard cell ASICs are ________ those for MPGAs.
A.	lower than
B.	about the same as
C.	higher than
D.	none of the above
Answer» D. none of the above

Discussion

8.	Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.
A.	1
B.
Answer» B.

Discussion

9.	The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.
A.	1
B.
Answer» B.

Discussion

10.	All inputs to the MAX7000S device and all macrocell outputs feed the ________.
A.	LUT
B.	PIA
C.	LAB
D.	PIA and LAB
Answer» C. LAB

Discussion

11.	Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
A.	AND array
B.	Look-up table
C.	OR array
D.	AND and OR array
Answer» C. OR array

Discussion

12.	The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.
A.	1
B.
Answer» C.

Discussion

13.	The final step in a design flow in which the logic design is implemented in the target device is called ________.
A.	design entry
B.	simulation
C.	downloading
D.	compiling
Answer» D. compiling

Discussion

14.	Expanders make it possible to increase the number of terms in a programmable SOP operation.
A.	1
B.
Answer» B.

Discussion

15.	The SRAM technology is volatile.
A.	1
B.
Answer» B.

Discussion

16.	Sum-of-products is two or more product terms that are NANDed together.
A.	1
B.
Answer» C.

Discussion

17.	In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.
A.	1
B.
Answer» B.

Discussion

18.	The flexibility of the GAL16V8 is in its ________.
A.	AND/OR array
B.	D flip-flops
C.	programmable output logic macro cells
D.	EEPROM
Answer» D. EEPROM

Discussion

19.	Gated arrays are ________ circuits that offer hundreds of thousands of gates.
A.	VLSI
B.	full custom
C.	LSI
D.	ULSI
Answer» E.

Discussion

20.	All I/O pins in the MAX7000S family have a tristate buffer.
A.	1
B.
Answer» B.

Discussion

21.	Schematic capture is a process performed by PLD software.
A.	1
B.
Answer» B.

Discussion

22.	The major structures in the MAX7000S are the ________ and ________.
A.	LUT, PIA
B.	FMUX, LAB
C.	LAB, PIA
D.	LUT, FMUX
Answer» D. LUT, FMUX

Discussion

23.	The architecture of a PAL differs slightly from that of a PROM.
A.	1
B.
Answer» B.

Discussion

24.	The SPLD classification includes the ________ PLD devices.
A.	earliest
B.	smallest
C.	largest
D.	newest
Answer» B. smallest

Discussion

25.	Most complex digital designs include a mix of different hardware categories.
A.	1
B.
Answer» B.

Discussion

26.	In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.
A.	1
B.
Answer» B.

Discussion

27.	The process or sequence of all operations carried out to ultimately program a target device is called the ________.
A.	graphic entry
B.	LAB
C.	downloading
D.	design flow
Answer» E.

Discussion

28.	A CPLD is basically a simplified PLD.
A.	1
B.
Answer» C.

Discussion

29.	A macrocell is ________.
A.	part of a PAL or GAL
B.	a type of one-time programmable SPLD
C.	an example of intellectual property
D.	a logic array block
Answer» B. a type of one-time programmable SPLD

Discussion

30.	Antifuse devices are volatile.
A.	1
B.
Answer» C.

Discussion

31.	VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.
A.	1
B.
Answer» B.

Discussion

32.	The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.
A.	4
B.	5
C.	6
D.	7
Answer» C. 6

Discussion

33.	The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.
A.	1
B.
Answer» C.

Discussion

34.	The GAL16V8 has architecture that is very similar to the ________ device.
A.	PAL
B.	PROM
C.	PLD
D.	SPLD
Answer» B. PROM

Discussion

35.	CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).
A.	1
B.
Answer» B.

Discussion

36.	Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________.
A.	HCPLDs
B.	full custom
C.	GAL
D.	FPLDs
Answer» C. GAL

Discussion

37.	A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.
A.	1
B.
Answer» C.

Discussion

38.	PLDs cannot meet all the possible requirements of complex digital circuitry.
A.	1
B.
Answer» C.

Discussion

39.	All inputs to the MAX7000S device and all macrocell outputs feed the PIA.
A.	1
B.
Answer» B.

Discussion

40.	In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.
A.	asynchronous reset, synchronous preset
B.	asynchronous preset, synchronous reset
C.	asynchronous clear, synchronous set
D.	asynchronous set, synchronous clear
Answer» B. asynchronous preset, synchronous reset

Discussion

41.	In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.
A.	1
B.
Answer» B.

Discussion

42.	The distinction between CPLDs and FPGAs is ________.
A.	well known
B.	very small
C.	often fuzzy
D.	very large
Answer» D. very large

Discussion

43.	The Boolean sum of the four product terms is called the sum-of-products.
A.	1
B.
Answer» B.

Discussion

44.	An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
A.	100-pin
B.	120-pin
C.	140-pin
D.	160-pin
Answer» E.

Discussion

45.	In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.
A.	a dot
B.	a bus
C.	a single line
D.	4 inputs
Answer» D. 4 inputs

Discussion

46.	Using a hardware solution for your digital system design is always faster than a software solution.
A.	1
B.
Answer» B.

Discussion

47.	________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.
A.	TTL
B.	CMOS
C.	ECL
D.	None of the above
Answer» B. CMOS

Discussion

48.	An application program in the development software package that controls the operation of the software is called a ________.
A.	compiler
B.	bed-of-nails
C.	boundary scan
D.	primitive
Answer» B. bed-of-nails

Discussion

49.	A GAL is a programmable/reprogrammable PAL.
A.	1
B.
Answer» B.

Discussion

50.	A PAL uses a programmable OR array followed by a fixed AND array.
A.	1
B.
Answer» C.

Discussion

Explore topic-wise MCQs in Digital Electronics.

The EPM 7128S is a(n) ________ device.

The GAL16V8 has eight dedicated input pins.

Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

The hard core portions of FPGAs are reprogrammable in the field.

FLEX10K devices are generally classified as ________.

The GAL22V10 has 12 outputs pins and 10 input pins.

Design costs for standard cell ASICs are ________ those for MPGAs.

Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.

The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.

All inputs to the MAX7000S device and all macrocell outputs feed the ________.

Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.

The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.

The final step in a design flow in which the logic design is implemented in the target device is called ________.

Expanders make it possible to increase the number of terms in a programmable SOP operation.

The SRAM technology is volatile.

Sum-of-products is two or more product terms that are NANDed together.

In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.

The flexibility of the GAL16V8 is in its ________.

Gated arrays are ________ circuits that offer hundreds of thousands of gates.

All I/O pins in the MAX7000S family have a tristate buffer.

Schematic capture is a process performed by PLD software.

The major structures in the MAX7000S are the ________ and ________.

The architecture of a PAL differs slightly from that of a PROM.

The SPLD classification includes the ________ PLD devices.

Most complex digital designs include a mix of different hardware categories.

In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.

The process or sequence of all operations carried out to ultimately program a target device is called the ________.

A CPLD is basically a simplified PLD.

A macrocell is ________.

Antifuse devices are volatile.

VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.

The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.

The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.

The GAL16V8 has architecture that is very similar to the ________ device.

CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).

Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________.

A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

PLDs cannot meet all the possible requirements of complex digital circuitry.

All inputs to the MAX7000S device and all macrocell outputs feed the PIA.

In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.

The distinction between CPLDs and FPGAs is ________.

The Boolean sum of the four product terms is called the sum-of-products.

An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.

In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.

Using a hardware solution for your digital system design is always faster than a software solution.

________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.

An application program in the development software package that controls the operation of the software is called a ________.

A GAL is a programmable/reprogrammable PAL.

A PAL uses a programmable OR array followed by a fixed AND array.

The major structures in the MAX7000S are the and .

In a GAL16V8, the D flip-flops contained in the OLMCs have and .