Explore topic-wise MCQs in Vlsi.

This section includes 5 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.

1.

The D Flip Flop implementation for PFD is:

A. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12a.png"><img alt="The D Flip Flop implementation for PFD - option a" class="alignnone size-full wp-image-162037" height="366" sizes="(max-width: 316px) 100vw, 316px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12a.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12a.png 316w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12a-259x300.png 259w" width="316"/></a>
B. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12b.png"><img alt="The D Flip Flop implementation for PFD - option b" class="alignnone size-full wp-image-162038" height="361" sizes="(max-width: 305px) 100vw, 305px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12b.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12b.png 305w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12b-253x300.png 253w" width="305"/></a>
C. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12c.png"><img alt="The D Flip Flop implementation for PFD - option c" class="alignnone size-full wp-image-162039" height="377" sizes="(max-width: 311px) 100vw, 311px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12c.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12c.png 311w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q12c-247x300.png 247w" width="311"/></a>
D. None of the mentioned
Answer» D. None of the mentioned
Discussion
2.

The correct input-output waveforms of Frequency detector:

A. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11a.png"><img alt="Input-output waveforms of Frequency detector - option a" class="alignnone size-full wp-image-162033" height="208" sizes="(max-width: 415px) 100vw, 415px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11a.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11a.png 415w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11a-300x150.png 300w" width="415"/></a>
B. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11b.png"><img alt="Input-output waveforms of Frequency detector - option b" class="alignnone size-full wp-image-162034" height="196" sizes="(max-width: 439px) 100vw, 439px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11b.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11b.png 439w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11b-300x134.png 300w" width="439"/></a>
C. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png"><img alt="Input-output waveforms of Frequency detector - option c" class="alignnone size-full wp-image-162035" height="156" sizes="(max-width: 399px) 100vw, 399px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png 399w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c-300x117.png 300w" width="399"/></a>
D. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11d.png"><img alt="Input-output waveforms of Frequency detector - option d" class="alignnone size-full wp-image-162036" height="164" sizes="(max-width: 431px) 100vw, 431px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11d.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11d.png 431w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11d-300x114.png 300w" width="431"/></a>
Answer» C. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png"><img alt="Input-output waveforms of Frequency detector - option c" class="alignnone size-full wp-image-162035" height="156" sizes="(max-width: 399px) 100vw, 399px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c.png 399w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q11c-300x117.png 300w" width="399"/></a>
Discussion
3.

If the input of type 1 PLL is a frequency step of w at t = 0, the change in phase at t = infinity is:

A. w
B. w/Kpd
C. w/Kpd.Kvco
D. None of the mentioned
Answer» D. None of the mentioned
Discussion
4.

Instead of Phase detection, if Frequency detector is used the drawback PLL would face is:

A. Finite difference between input and output frequency
B. Equality cannot be established if PLL compared input and output frequency rather than pulses
C. Error between Vin and Vout cannot be removed
D. All of the mentioned
Answer» E.
Discussion
5.

The block diagram of basic PLL consists of:

A. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q3.png"><img alt="The block diagram of basic PLL - option a" class="alignnone size-full wp-image-162025" height="160" sizes="(max-width: 524px) 100vw, 524px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q3.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q3.png 524w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q3-300x92.png 300w" width="524"/></a>
B. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7b.png"><img alt="The block diagram of basic PLL - option b" class="alignnone size-full wp-image-162031" height="103" sizes="(max-width: 379px) 100vw, 379px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7b.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7b.png 379w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7b-300x82.png 300w" width="379"/></a>
C. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7c.png"><img alt="The block diagram of basic PLL - option c" class="alignnone size-full wp-image-162032" height="108" sizes="(max-width: 547px) 100vw, 547px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7c.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7c.png 547w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-phase-lock-loops-q7c-300x59.png 300w" width="547"/></a>
D. None of the Mentioned
Answer» D. None of the Mentioned
Discussion