Explore topic-wise MCQs in Vlsi.

This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.

1.

LOAD_CAPACITANCE_CAN_BE_MINIMIZED_BY?$

A. increasing A
B. decreasing A
C. increasing Psd
D. does not depend on A
Answer» C. increasing Psd
Discussion
2.

Rise time and fall time can be equalized by$

A. βn = βp
B. βn = 2βp
C. βp = 2βn
D. βn = 1/2βp
Answer» B. ‚âà√≠‚Äö√¢¬ßn = 2‚âà√≠‚Äö√¢¬ßp
Discussion
3.

Switching power dissipation can be given a?

A. Cl x Vdd x f
B. Vdd<sup>2</sup> x f
C. Cl x Vdd<sup>2</sup>
D. Cl x Vdd<sup>2</sup> x f
Answer» E.
Discussion
4.

The ratio of Wp/Wn can be given as

A. 1:2
B. 2:1
C. 1:1
D. 2:2
Answer» D. 2:2
Discussion
5.

The area of CMOS inverter is proportional to

A. area of n device
B. area of p device
C. total area of n and p device
D. square of minimum feature size
Answer» D. square of minimum feature size
Discussion
6.

For a regular 8:1 inverter the transition delay is given as

A. 10Ʈ
B. 20Ʈ
C. 21Ʈ
D. 25Ʈ
Answer» D. 25‚Äö√†√ú‚àö√ú
Discussion
7.

In minimum size nMOS 8:1 inverter the logic 0 to 1 transition delay is given as

A. 5Ʈ
B. 20Ʈ
C. 40Ʈ
D. 50Ʈ
Answer» D. 50‚Äö√†√ú‚àö√ú
Discussion
8.

In inverter during logic 1 to 0 transition, capacitance discharges at

A. pull-up resistance
B. pull-down resistance
C. both pull-up and pull-down
D. at gate
Answer» C. both pull-up and pull-down
Discussion
9.

When does longest delay occur in 8:1 inverters?

A. during 1 to 0 transition
B. during 0 to 1 transition
C. during faster speed
D. delays are always short
Answer» C. during faster speed
Discussion
10.

Reduction in power dissipation can be brought by

A. increasing transistor area
B. decreasing transistor area
C. increasing transistor feature size
D. decreasing transistor feature size
Answer» B. decreasing transistor area
Discussion