170 + Mcqs in Memory Organization Mcqs Page 3 McqOptions

101.	For reducing the frequency on replacement of write-back blocks, the commonly used feature, is known as
A.	Hit miss
B.	Index field
C.	Write-through
D.	Dirty bit
Answer» E.

Discussion

102.	A direct-mapped cache having a size of N and has the miss rate same as a two-way set-associative cache, of size
A.	N
B.	N*2
C.	N/2
D.	N^2
Answer» D. N^2

Discussion

103.	The block placement strategy, is if set associative/direct mapped, then this miss is called
A.	Hit miss
B.	Cache miss
C.	Conflict miss
D.	Hit rate
Answer» D. Hit rate

Discussion

104.	When Cycle per instruction is 1.0, data accesses are 50% of the total instructions, and the miss penalty is 25clock-cycles and the miss rate having 2%, then the computer would the faster as,
A.	1.25
B.	1.45
C.	1.75
D.	1.85
Answer» D. 1.85

Discussion

105.	The address spaces are typically broken into the fixed-size blocks, called
A.	Registers
B.	Stacks
C.	Pages
D.	Frames
Answer» D. Frames

Discussion

106.	The rate of no of misses in a cache which is divided by whole number of memory-accesses, to the cache, is known as
A.	Local miss rate
B.	Global miss rate
C.	Hit rate
D.	Miss rate
Answer» B. Global miss rate

Discussion

107.	Assume that the hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 KB cache will be having access-time of
A.	6.027 clock cycles
B.	8.077 clock cycles
C.	7.027 clock cycles
D.	8.027 clock cycles
Answer» E.

Discussion

108.	The virtual memory producing the virtual-addresses, are translated by
A.	Logical addresses
B.	Local addresses
C.	Physical addresses
D.	All above
Answer» D. All above

Discussion

109.	The most obvious architectural parameter is the
A.	Physical pages
B.	Page sizes
C.	Page fault
D.	Block size
Answer» C. Page fault

Discussion

110.	The time of CPU can be modeled as
A.	(CPU execution clock cycles + Memory stall clock cycles) - Clock cycle time
B.	(CPU execution clock cycles x Memory stall clock cycles) + Clock cycle time
C.	(CPU execution clock cycles + Memory stall clock cycles)
D.	(CPU execution clock cycles / Memory stall clock cycles)
Answer» D. (CPU execution clock cycles / Memory stall clock cycles)

Discussion

111.	The processor protection structure expand memory access protection from two levels to many, the added ones are
A.	Rings
B.	Frames
C.	Pages
D.	Blocks
Answer» B. Frames

Discussion

112.	IA-32 allows the operating system to maintain the protection level of the called
A.	Rings
B.	Frames
C.	Pages
D.	Routine
Answer» E.

Discussion

113.	Per memory reference, the miss-rate can be turned into the per instruction misses rate by
A.	Miss rate= Memory accesses/ instructions
B.	Miss rate= Memory accesses* instructions
C.	Miss rate= Memory accesses-instructions
D.	Miss rate= Memory accesses+ instructions
Answer» B. Miss rate= Memory accesses* instructions

Discussion

114.	The field that is not found in paged systems, which establishes theupper bound of valid offsets for segments is called
A.	Limit field
B.	Valid field
C.	Fault bit
D.	Frame
Answer» B. Valid field

Discussion

115.	A common optimization for reducing write stalls is a
A.	Write buffer
B.	Write-back
C.	Read stall
D.	Write stall
Answer» B. Write-back

Discussion

116.	Address translation cache is referred to as a
A.	Rephrasing
B.	Cache buffer
C.	Translation buffer
D.	Relocation
Answer» D. Relocation

Discussion

117.	Cutting of physical-memory into the form of blocks and allocating them to different processes, the stated technique is known as
A.	Read back
B.	Cache miss
C.	Cache hit
D.	Virtual memory
Answer» E.

Discussion

118.	If the processor is not willing in the cycle for retiring the maximum number of instructions; it is said to be
A.	In a stalled clock cycle
B.	Write-back
C.	Write-through
D.	Read through
Answer» B. Write-back

Discussion

119.	The security loopholes, prevents by not allowing the user process to ask the operating system to access somethingindirectly are known as
A.	Blocks
B.	Frames
C.	Trojan horses
D.	Routines
Answer» D. Routines

Discussion

120.	When the processor is waiting for write instruction to complete during the write-through process, the processor is said to
A.	Read back
B.	Write-back
C.	Read stall
D.	Write stall
Answer» E.

Discussion

121.	If a set has n blocks, the cache placement is then called
A.	2-way set distributive
B.	2-way set associative
C.	N-way setting
D.	N-way set associative
Answer» E.

Discussion

122.	The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?
A.	256 words
B.	512 words
C.	1024 words
D.	128 words
Answer» B. 512 words

Discussion

123.	If a block can be placed at every location in the cache, this cache is said to be
A.	Indirectly mapped
B.	Directly mapped
C.	Fully associative
D.	Partially associative
Answer» D. Partially associative

Discussion

124.	For recording, was the block written, the Opteron keeps
A.	1 dirty bit per block
B.	2 dirty bits per block
C.	3 dirty bits per block
D.	4 dirty bits per block
Answer» B. 2 dirty bits per block

Discussion

125.	The information when is written in the cache, both to the block in the cache and the block present in the lower-level memory, refers to
A.	Miss rate
B.	Write-back
C.	Write-through
D.	Dirty bit
Answer» D. Dirty bit

Discussion

126.	Average access time of memory for having memory-hierarchy performance is given as
A.	Average memory access time = Hit time + Miss rate
B.	Average memory access time = Hit time + Miss rate
C.	Average memory access time = Hit time + Miss rate + Miss penalty
D.	Average memory access time = Hit time + Miss rate - Miss penalty
Answer» C. Average memory access time = Hit time + Miss rate + Miss penalty

Discussion

127.	As segment or a page is normally used for block, page-fault and the address-fault is used for
A.	Hit
B.	Miss
C.	Cache
D.	Stack
Answer» C. Cache

Discussion

128.	The block frame address are divided into the
A.	Tag field
B.	Index field
C.	Stack field
D.	Both a and b
Answer» E.

Discussion

129.	The increase in the width of the cache address tag, can be done with the
A.	Process-identity tag
B.	Process-identifier term
C.	Process-identifier tag
D.	Process-identify tag
Answer» D. Process-identify tag

Discussion

130.	The name given to the first or highest level of the memory-hierarchy, is known as
A.	Memory
B.	Cache
C.	Flash memory
D.	Registers
Answer» C. Flash memory

Discussion

131.	The physical-address that is coming to the cache is further divided into field/s:
A.	Block address
B.	Block offset
C.	Write-through
D.	Both a and b
Answer» E.

Discussion

132.	If the cache is not able for containing all the blocks needed while execution, the miss is then known as
A.	Hit miss
B.	Cache miss
C.	Cache hit
D.	Hit rate
Answer» C. Cache hit

Discussion

133.	When the victim buffer is totally full, the cache must
A.	Be full
B.	Be empty
C.	Wait
D.	Move next
Answer» D. Move next

Discussion

134.	10% stores and 26% loads instruction for MIPS programs, to make writes
A.	5%
B.	10%
C.	15%
D.	20%
Answer» C. 15%

Discussion

135.	Larger blocks increases the conflict-misses and the capacity-misses, whenever the cache is
A.	Great
B.	Small
C.	Large
D.	Corrupt
Answer» C. Large

Discussion

136.	The page table level that says if page has been modified, is known as
A.	Presence
B.	Read/write
C.	Page size
D.	Dirty
Answer» E.

Discussion

137.	Data structure, maintaining the addresses of physical-pages, typically takes the form of a
A.	Page size
B.	Page table
C.	Queue
D.	Stack
Answer» C. Queue

Discussion

138.	The matching tag sends the corresponding physical address through effectively a
A.	40:1 multiplexor
B.	20:1 multiplexor
C.	20:2 multiplexor
D.	30:1 multiplexor
Answer» B. 20:1 multiplexor

Discussion

139.	Forget to accounting the byte addressing or the cache block-size, in processing a cache is a
A.	Pitfall
B.	Fallacy
C.	Fully associative
D.	Set associative
Answer» B. Fallacy

Discussion

140.	The principle of locality that was used; implementing memory of the computer as
A.	Locality in time
B.	Locality in space
C.	Memory hierarchy
D.	Temporal locality
Answer» D. Temporal locality

Discussion

141.	The program of copying address of PTE into temp $k1 would be executed with the instruction
A.	Mfc0 $k1,Constant
B.	Mfc1 $k1,Context
C.	Mfc0 $k1,Context
D.	Mfc0 $k2,Context
Answer» D. Mfc0 $k2,Context

Discussion

142.	A field in the memory hierarchy table that indicates the associated block, is called a
A.	Hit bit
B.	Valid bit
C.	Valid data
D.	Hit time
Answer» C. Valid data

Discussion

143.	A virtual-memory block is known as page, and a virtual-memory miss is called a
A.	Page miss
B.	Hit miss
C.	Page fault
D.	Memory fault
Answer» D. Memory fault

Discussion

144.	Latency clock rate of the AMD operation is,
A.	2
B.	3
C.	4
D.	5
Answer» C. 4

Discussion

145.	The decimal address having reference 22 will have a Binary address of reference
A.	10111two
B.	11110two
C.	10100two
D.	10110two
Answer» E.

Discussion

146.	Cache misses created by the 1st access to a block, that was not in the cache, is known as
A.	Cold-start misses
B.	Compulsory misses
C.	Capacity misses
D.	Both a and b
Answer» E.

Discussion

147.	A situation in which the same object is being accessed by two addresses, is referred to as
A.	Aliasing
B.	Hit miss
C.	Valid data
D.	Page miss
Answer» B. Hit miss

Discussion

148.	The Cortex-A8 known as configurable core, which supports the computer instruction set architecture of
A.	ARMv6
B.	ARMv7
C.	ARMv8
D.	ARMv9
Answer» C. ARMv8

Discussion

149.	One-half of the address is first sent during the
A.	Row access strobe
B.	Column access strobe
C.	Column access cycle
D.	Row access time
Answer» B. Column access strobe

Discussion

150.	Switching from one process to another. This swapping is called a
A.	Process switch
B.	Context switch
C.	Exchange
D.	Both a and b
Answer» E.

Discussion

Explore topic-wise MCQs in Organization and Architecture Mcqs.

For reducing the frequency on replacement of write-back blocks, the commonly used feature, is known as

A direct-mapped cache having a size of N and has the miss rate same as a two-way set-associative cache, of size

The block placement strategy, is if set associative/direct mapped, then this miss is called

When Cycle per instruction is 1.0, data accesses are 50% of the total instructions, and the miss penalty is 25clock-cycles and the miss rate having 2%, then the computer would the faster as,

The address spaces are typically broken into the fixed-size blocks, called

The rate of no of misses in a cache which is divided by whole number of memory-accesses, to the cache, is known as

Assume that the hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 KB cache will be having access-time of

The virtual memory producing the virtual-addresses, are translated by

The most obvious architectural parameter is the

The time of CPU can be modeled as

The processor protection structure expand memory access protection from two levels to many, the added ones are

IA-32 allows the operating system to maintain the protection level of the called

Per memory reference, the miss-rate can be turned into the per instruction misses rate by

The field that is not found in paged systems, which establishes theupper bound of valid offsets for segments is called

A common optimization for reducing write stalls is a

Address translation cache is referred to as a

Cutting of physical-memory into the form of blocks and allocating them to different processes, the stated technique is known as

If the processor is not willing in the cycle for retiring the maximum number of instructions; it is said to be

The security loopholes, prevents by not allowing the user process to ask the operating system to access somethingindirectly are known as

When the processor is waiting for write instruction to complete during the write-through process, the processor is said to

If a set has n blocks, the cache placement is then called

The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?

If a block can be placed at every location in the cache, this cache is said to be

For recording, was the block written, the Opteron keeps

The information when is written in the cache, both to the block in the cache and the block present in the lower-level memory, refers to

Average access time of memory for having memory-hierarchy performance is given as

As segment or a page is normally used for block, page-fault and the address-fault is used for

The block frame address are divided into the

The increase in the width of the cache address tag, can be done with the

The name given to the first or highest level of the memory-hierarchy, is known as

The physical-address that is coming to the cache is further divided into field/s:

If the cache is not able for containing all the blocks needed while execution, the miss is then known as

When the victim buffer is totally full, the cache must

10% stores and 26% loads instruction for MIPS programs, to make writes

Larger blocks increases the conflict-misses and the capacity-misses, whenever the cache is

The page table level that says if page has been modified, is known as

Data structure, maintaining the addresses of physical-pages, typically takes the form of a

The matching tag sends the corresponding physical address through effectively a

Forget to accounting the byte addressing or the cache block-size, in processing a cache is a

The principle of locality that was used; implementing memory of the computer as

The program of copying address of PTE into temp $k1 would be executed with the instruction

A field in the memory hierarchy table that indicates the associated block, is called a

A virtual-memory block is known as page, and a virtual-memory miss is called a

Latency clock rate of the AMD operation is,

The decimal address having reference 22 will have a Binary address of reference

Cache misses created by the 1st access to a block, that was not in the cache, is known as

A situation in which the same object is being accessed by two addresses, is referred to as

The Cortex-A8 known as configurable core, which supports the computer instruction set architecture of

One-half of the address is first sent during the

Switching from one process to another. This swapping is called a