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MCQOPTIONS
This section includes 170 Mcqs, each offering curated multiple-choice questions to sharpen your Organization and Architecture Mcqs knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______. |
| A. | Level 1 cache |
| B. | Level 2 cache |
| C. | Registers |
| D. | TLB |
| Answer» B. Level 2 cache | |
| 2. |
The memory address range to which RAM will respond |
| A. | 0000 H to 1 FFF H |
| B. | 0000 H to 5FFF H |
| C. | 4000 H to 5FFF H |
| D. | 3000 H to FFFF H |
| Answer» D. 3000 H to FFFF H | |
| 3. |
How many addresses are required for 25 x 40 video RAM ? |
| A. | 1020 |
| B. | 1920 |
| C. | 1000 |
| D. | 1500 |
| Answer» D. 1500 | |
| 4. |
Four memory chips of 16 x 4 size have their address bases connected together. The system will be of size |
| A. | 64 x 64 |
| B. | 16 x 16 |
| C. | 32 x 16 |
| D. | 256 x I |
| Answer» C. 32 x 16 | |
| 5. |
Property of locality of reference may fail, if a program has |
| A. | Many conditional jumps |
| B. | Many unconditional jumps |
| C. | Many operands |
| D. | Many Operators |
| Answer» D. Many Operators | |
| 6. |
In a virtual memory system the address space specified by the address lines of the CPU must be than the physical memory size and than the secondary storage size. |
| A. | Smaller, smaller |
| B. | Smaller, larger |
| C. | Larger, smaller |
| D. | Larger, larger |
| Answer» D. Larger, larger | |
| 7. |
Memory refreshing may be done |
| A. | By the CPU that contains a special refresh counter |
| B. | By an external refresh controller |
| C. | Either by the CPU or by an external refresh controller |
| D. | None of these |
| Answer» C. Either by the CPU or by an external refresh controller | |
| 8. |
How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16? |
| A. | 64 |
| B. | 32 |
| C. | 128 |
| D. | 16 |
| Answer» C. 128 | |
| 9. |
The DMA controller is connected to the ____ |
| A. | Processor BUS |
| B. | System BUS |
| C. | External BUS |
| D. | None of the above |
| Answer» C. External BUS | |
| 10. |
How many address bits are required to represent a 32 K memory |
| A. | 10 bits |
| B. | 12 bits |
| C. | 14 bits |
| D. | 16 bits |
| Answer» E. | |
| 11. |
To overcome the conflict over the possession of the BUS we use ______. |
| A. | Optimizers |
| B. | BUS arbitrators |
| C. | Multiple BUS structure |
| D. | None of the above |
| Answer» C. Multiple BUS structure | |
| 12. |
The registers of the controller are ______. |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 13. |
When process requests for a DMA transfer , |
| A. | Then the process is temporarily suspended |
| B. | The process continues execution |
| C. | Another process gets executed |
| D. | Both a and c |
| Answer» E. | |
| 14. |
Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________. |
| A. | 0.05 |
| B. | 0.06 |
| C. | 0.07 |
| D. | 0.08 |
| Answer» B. 0.06 | |
| 15. |
A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits. |
| A. | 12 |
| B. | 14 |
| C. | 16 |
| D. | 18 |
| Answer» C. 16 | |
| 16. |
How many address bits are required to represent 4K memory |
| A. | 5 bits |
| B. | 12 bits |
| C. | 8 bits |
| D. | 10 bits |
| Answer» C. 8 bits | |
| 17. |
Which of the following memories stores the most number of bits? |
| A. | 64K 8 memory |
| B. | 1M 8 memory |
| C. | 32M 8 memory |
| D. | 64 6 memory |
| Answer» D. 64 6 memory | |
| 18. |
For the synchronization of the read head, we make use of a _______. |
| A. | Framing bit |
| B. | Synchronization bit |
| C. | Clock |
| D. | Dirty bit |
| Answer» D. Dirty bit | |
| 19. |
The method of placing the heads and the discs in an air tight environment is called as ______. |
| A. | RAID Arrays |
| B. | ATP tech |
| C. | Winchester technology |
| D. | Fleming reduction |
| Answer» D. Fleming reduction | |
| 20. |
The transfer of large chunks of data with the involvement of the processor is done by _______ . |
| A. | DMA controller |
| B. | Arbitrator |
| C. | User system programs |
| D. | None of the above |
| Answer» B. Arbitrator | |
| 21. |
The BOOT sector files of the system are stored in _____ . |
| A. | Harddisk |
| B. | ROM |
| C. | RAM |
| D. | Fast solid state chips in the motherboard |
| Answer» C. RAM | |
| 22. |
For estimating the accessing time and energy consumption of cache structure on CMOS microprocessors, the program used is |
| A. | CAD |
| B. | CACTI |
| C. | CACT |
| D. | DAE |
| Answer» C. CACT | |
| 23. |
A reliable high-end processor: the Intel Core i7 has capability of generating two data memory references per core at every clock cycle; with 4 cores and a 3.2 GHz clock-rate, the data memory generated by i7 is, |
| A. | 35.6 billion 64-bit data memory/sec |
| B. | 25.6 billion 64-bit data memory/sec |
| C. | 55.6 billion 64-bit data memory/sec |
| D. | 22.6 billion 64-bit data memory/sec |
| Answer» C. 55.6 billion 64-bit data memory/sec | |
| 24. |
Time for replacing the block from memory, is referred to as |
| A. | Hit penalty |
| B. | Miss penalty |
| C. | Hit rate |
| D. | Hit miss |
| Answer» C. Hit rate | |
| 25. |
For translating the virtual address, from the micro-processor to a physical-address for accessing memory, the memory used in this task is |
| A. | Main memory |
| B. | RAM |
| C. | ROM |
| D. | Cache |
| Answer» E. | |
| 26. |
The letters of SRAM, stands for |
| A. | Sequential |
| B. | System |
| C. | Stats |
| D. | Static |
| Answer» E. | |
| 27. |
Virtual machines provide an abstraction that is used for running the complete software stack, this stated abstraction is known as |
| A. | Managing software |
| B. | Managing hardware |
| C. | Supervision |
| D. | Row access time |
| Answer» B. Managing hardware | |
| 28. |
The index of instruction cache is |
| A. | 2Index= Cache size- Block size |
| B. | 2Index= Cache size/ Block size + Set associativity |
| C. | 2Index= Cache size+ Block size |
| D. | 2Index= Cache size/ Block size |
| Answer» E. | |
| 29. |
For paying an extra level of indirection for each memory access, the Virtual machine monitor maintains a |
| A. | Shadow page table |
| B. | Stack table |
| C. | Memory stack |
| D. | Queue |
| Answer» B. Stack table | |
| 30. |
Storing the arrays as row by row order, is referred to as |
| A. | Row major order |
| B. | Column major order |
| C. | Row order |
| D. | Column order |
| Answer» B. Column major order | |
| 31. |
Two processors running one is user process, other is operating system process, the latter is called |
| A. | Kernel process |
| B. | Supervisor process |
| C. | System process |
| D. | Both a and b |
| Answer» E. | |
| 32. |
The software that supports Virtual machines, is called a |
| A. | Virtual machine monitor |
| B. | Hypervisor |
| C. | Kernel |
| D. | Both a and b |
| Answer» E. | |
| 33. |
Average memory access time can be calculated as |
| A. | Average memory access time = Hit time + Miss rate |
| B. | Average memory access time = Hit time - Miss rate |
| C. | Average memory access time = Hit time + Miss rate _ Miss penalty |
| D. | Average memory access time = Miss rate |
| Answer» B. Average memory access time = Hit time - Miss rate | |
| 34. |
Dual inline memory modules (DIMMs) typically contains |
| A. | 2 to 16 DRAMs |
| B. | 1 to 15 DRAMs |
| C. | 4 to 8 DRAMs |
| D. | 2 to 12 DRAMs |
| Answer» E. | |
| 35. |
If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be |
| A. | 2^9 |
| B. | 2^13 |
| C. | 2^15 |
| D. | 2^17 |
| Answer» C. 2^15 | |
| 36. |
A direct-mapped cache has only 1 block/set and a |
| A. | Partially associative |
| B. | Half associative |
| C. | Fully associative |
| D. | Fully distributive |
| Answer» D. Fully distributive | |
| 37. |
Blocking optimization is used to improve temporal locality, for reduce |
| A. | Hit miss |
| B. | Misses |
| C. | Hit rate |
| D. | Cache misses |
| Answer» C. Hit rate | |
| 38. |
GDRAMs or GSDRAMs are known as Dynamic DRAMs, also called |
| A. | Graphics or Graphics Synchronous DRAMs |
| B. | Gross or Gross Synchronous DRAMs |
| C. | Graphics or Graphics Static DRAMs |
| D. | Gross or Gross Static DRAMs |
| Answer» B. Gross or Gross Synchronous DRAMs | |
| 39. |
1000 MIPS processor for running programs successfully must have at-least |
| A. | 10MB of memory |
| B. | 100MB of memory |
| C. | 1000MB of memory |
| D. | 10GB of memory |
| Answer» D. 10GB of memory | |
| 40. |
An architecture, allowing the Virtual machines for executing directly on the hardware , deserves the title |
| A. | Manageable |
| B. | Scalable |
| C. | Virtualizable |
| D. | Compatible |
| Answer» D. Compatible | |
| 41. |
Advanced cache optimization has been divided into |
| A. | 2 categories |
| B. | 3 categories |
| C. | 5 categories |
| D. | 7 categories |
| Answer» D. 7 categories | |
| 42. |
Combination of instruction cycle and execution cycle is known as |
| A. | Fetching |
| B. | Decoding |
| C. | Executing |
| D. | Machine cycle |
| Answer» E. | |
| 43. |
The instruction miss which is serviced by the main memory, has total latency, approximately of |
| A. | 35 processor cycles |
| B. | 40 processor cycles |
| C. | 42 processor cycles |
| D. | 45 processor cycles |
| Answer» B. 40 processor cycles | |
| 44. |
The time when a read instruction is requested and when the desired instruction arrives, is referred to as |
| A. | Cycle time |
| B. | Access time |
| C. | Hit time |
| D. | Miss time |
| Answer» C. Hit time | |
| 45. |
A processor for going from a user mode to a supervisor mode, needs |
| A. | System call |
| B. | Kernel call |
| C. | Supervisor call |
| D. | Digital call |
| Answer» B. Kernel call | |
| 46. |
A mapping that works well for spreading the block addresses sequentially all across the banks, are called |
| A. | Sequential interleaving |
| B. | Spatial interleaving |
| C. | Sequential interaction |
| D. | Sequential interchange |
| Answer» B. Spatial interleaving | |
| 47. |
CPU performance is often measured in |
| A. | MIPS |
| B. | BIPS |
| C. | Both a and b |
| D. | MBPS |
| Answer» D. MBPS | |
| 48. |
Cells of computer memory are organized into a group of |
| A. | 8 bits |
| B. | 5 bits |
| C. | 12 bits |
| D. | 4 bits |
| Answer» B. 5 bits | |
| 49. |
Memory of computer which is used to speed up the computer processing is |
| A. | ROM |
| B. | Cache memory |
| C. | BIOS |
| D. | RAM |
| Answer» C. BIOS | |
| 50. |
Main purpose of computer secondary storage device is to |
| A. | Calculate data |
| B. | Temporary store data |
| C. | Permanently store data |
| D. | Output of information |
| Answer» D. Output of information | |