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MCQOPTIONS
This section includes 170 Mcqs, each offering curated multiple-choice questions to sharpen your Organization and Architecture Mcqs knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
Process of storing programs and data in a computer memory is called |
| A. | CPU |
| B. | Data processing |
| C. | Fixed disk |
| D. | Stored-program concept |
| Answer» E. | |
| 52. |
Which of the following is not a type of computer memory? |
| A. | DRAM |
| B. | SRAM |
| C. | ROM |
| D. | FRAM |
| Answer» E. | |
| 53. |
Memory space in a computer is used to |
| A. | Hold applications |
| B. | Hold information temporarily |
| C. | Provide additional speed when needed |
| D. | All of these |
| Answer» E. | |
| 54. |
Working area of computer is |
| A. | Hard disk |
| B. | Main memory |
| C. | Floppy disk |
| D. | Hardware |
| Answer» C. Floppy disk | |
| 55. |
Computer memory is made up of |
| A. | Set of wires |
| B. | Set of circuits |
| C. | Cells |
| D. | Set of ports |
| Answer» D. Set of ports | |
| 56. |
If computer memory location is to be read, CPU places address in |
| A. | MAR |
| B. | MBR |
| C. | PC |
| D. | DOS |
| Answer» B. MBR | |
| 57. |
Memory of a computer which is used to store programs and data that are being executed is termed as |
| A. | Main memory |
| B. | Secondary memory |
| C. | RAM |
| D. | ROM |
| Answer» B. Secondary memory | |
| 58. |
Hit-rate of the processor is the memory fraction, found in |
| A. | DRAM |
| B. | SRAM |
| C. | Magnetic disk |
| D. | Cache |
| Answer» E. | |
| 59. |
Total bits for a direct-mapped cache with data of 16 KB and blocks of 4-word, assuming a 32-bit address are |
| A. | 142K bits |
| B. | 143 K bits |
| C. | 145K bits |
| D. | 147K bits |
| Answer» E. | |
| 60. |
The address location in the main memory, is referred to as |
| A. | Logical address |
| B. | Physical address |
| C. | Static address |
| D. | Block associative |
| Answer» C. Static address | |
| 61. |
Blocks to be placed at the upper level of the hierarchy scheme used, is from direct memory to |
| A. | Set definitive |
| B. | Block associative |
| C. | Fully associative |
| D. | Set associative |
| Answer» E. | |
| 62. |
Scheme having set, in the cache as a group of blocks, is known as |
| A. | Set distributive |
| B. | Principle of locality |
| C. | Set associative |
| D. | None of above |
| Answer» D. None of above | |
| 63. |
The subtraction of hit rate (1-hit rate) is known as |
| A. | Hit time |
| B. | Miss rate |
| C. | Miss penalty |
| D. | Cache |
| Answer» C. Miss penalty | |
| 64. |
If an item is referenced once, then it again be referenced soon; given statement is stated by |
| A. | Temporal locality |
| B. | Spatial locality |
| C. | Temporary locality |
| D. | Spectral Locality |
| Answer» B. Spatial locality | |
| 65. |
To help the operating system estimate LRU, many processors provide a |
| A. | Use bit |
| B. | Reference bit |
| C. | Fault bit |
| D. | Both a and b |
| Answer» E. | |
| 66. |
The policy for memory hierarchies: L1 data are never found in an L2 cache, refers to |
| A. | Write buffer |
| B. | Multilevel exclusion |
| C. | Write-through |
| D. | Multilevel inclusion |
| Answer» C. Write-through | |
| 67. |
The 64-bit virtual address of the AMD64 architecture is mapped onto |
| A. | 64 bits physical addresses |
| B. | 32 bits physical addresses |
| C. | 52 bits physical addresses |
| D. | 128 bits physical addresses |
| Answer» D. 128 bits physical addresses | |
| 68. |
A better measurement of performance of memory-hierarchy is the |
| A. | Average memory access time |
| B. | Average memory hit rate |
| C. | Average memory miss rate |
| D. | Write stall |
| Answer» B. Average memory hit rate | |
| 69. |
When the computer processor does not get a data item it requires in the cache, then the problem is known as |
| A. | Cache miss |
| B. | Cache hit |
| C. | File caches |
| D. | Name cache |
| Answer» B. Cache hit | |
| 70. |
To restrict entry into others |
| A. | Call gate |
| B. | Frame gate |
| C. | Jump |
| D. | None of above |
| Answer» B. Frame gate | |
| 71. |
Equivalent to the PTE valid bit, used to indicate the valid translation is refered to as |
| A. | Base field |
| B. | Present bit |
| C. | Access bit |
| D. | Attributes field |
| Answer» C. Access bit | |
| 72. |
To provide for protected sharing, half of the address space is shared by all processes and half is unique to each process, called |
| A. | Global address space |
| B. | Local address space |
| C. | Address bit |
| D. | Both a and b |
| Answer» E. | |
| 73. |
When the processor gets the requested data items from the cache, it is called a |
| A. | File caches |
| B. | Name cache |
| C. | Cache hit |
| D. | Registers |
| Answer» D. Registers | |
| 74. |
At any instant it is possible to switch from one process to another, this exchange is called a |
| A. | Process switch |
| B. | Context switch |
| C. | Swapping |
| D. | Both a and b |
| Answer» E. | |
| 75. |
Caches containing either instructions or data, is referred to the term |
| A. | Unified |
| B. | Mixed |
| C. | Wait |
| D. | Both a and b |
| Answer» E. | |
| 76. |
Hardware solutions for the synonym problems, are called |
| A. | Aliasing |
| B. | Anti-aliasing |
| C. | Hit rate |
| D. | Miss rate |
| Answer» C. Hit rate | |
| 77. |
If the entry is 8 bytes long, each page table has 512 entries, and the Opteron has 4 KB pages. Each of the four level fields are 9 bits long, and the page offset is 12 bits, then the sign extended would be |
| A. | 16 bits |
| B. | 32 bits |
| C. | 64 bits |
| D. | 128 bits |
| Answer» B. 32 bits | |
| 78. |
Fixed-size blocks known as pages, and those having variable-size blocks are known as |
| A. | Segment |
| B. | Page size |
| C. | Physical addresses |
| D. | Virtual memory |
| Answer» B. Page size | |
| 79. |
If going fully associative, refers to the |
| A. | Fully associative |
| B. | No conflict |
| C. | Fully conflicted |
| D. | Partialy associative |
| Answer» C. Fully conflicted | |
| 80. |
For reducing the chance of throwing the information which soon will be needed, this technique used is |
| A. | Least recently used |
| B. | Random |
| C. | First in, first out |
| D. | First in, last out |
| Answer» B. Random | |
| 81. |
The natural policy uses for the memory hierarchies: L1 data of cache are always present in L2 level of cache, refers to |
| A. | Write buffer |
| B. | Read buffer |
| C. | Write-through |
| D. | Multilevel inclusion |
| Answer» E. | |
| 82. |
The ratio of cache accesses, results in a miss is known as |
| A. | Hit miss |
| B. | Hit rate |
| C. | File caches |
| D. | Miss rate |
| Answer» E. | |
| 83. |
AMD64 requires that the upper 16 bits of the virtual address be just the sign extension of the lower 48 bits, which it calls |
| A. | Rephrasing |
| B. | Canonical form |
| C. | Trojan horses |
| D. | Block size |
| Answer» C. Trojan horses | |
| 84. |
Larger cache-size, larger block-size, and higher associativity, refers to the |
| A. | Read back |
| B. | Reducing the time to hit in the cache |
| C. | Reducing the miss penalty |
| D. | Reducing the miss rate |
| Answer» E. | |
| 85. |
A small page size will result in less wasted storage when a contiguous region of virtualmemory is not equal in size to a multiple of the page size, this unused memory is known as |
| A. | Segmentation |
| B. | External fragmentation |
| C. | Internal fragmentation |
| D. | All above |
| Answer» D. All above | |
| 86. |
Significant percentage of the spent time in moving data in two levels in the memory hierarchy, then the memory-hierarchy is said to |
| A. | Thrash |
| B. | Mixed |
| C. | Averaging |
| D. | Write stall |
| Answer» B. Mixed | |
| 87. |
The cache term is now applied when a buffering is employed for reusing commonly occurring items, for example |
| A. | File caches |
| B. | Name cache |
| C. | Flash memory |
| D. | Both a and b |
| Answer» E. | |
| 88. |
If each block having one place to be appear in the cache, this cache is said to be |
| A. | Indirectly mapped |
| B. | Directly mapped |
| C. | Pages |
| D. | Registers |
| Answer» C. Pages | |
| 89. |
In a direct-mapped cache of eight words (1)10 (00001two) and (29)10 (11101two) map to locations |
| A. | 0ten (001two) and 5ten (101two) |
| B. | 1ten (001two) and 4ten (101two) |
| C. | 1ten (001two) and 5ten (101two) |
| D. | 1ten (001two) and 6ten (101two) |
| Answer» D. 1ten (001two) and 6ten (101two) | |
| 90. |
The levels between the CPU and main memory were given a name of |
| A. | Hit time |
| B. | Miss rate |
| C. | Locality in time |
| D. | Cache |
| Answer» E. | |
| 91. |
Allowing the processor for continuing execution of instructions, that access data-cache while having cache miss, is known as |
| A. | Nonblocking cache |
| B. | Blocking cache |
| C. | Cache buffer |
| D. | None of above |
| Answer» B. Blocking cache | |
| 92. |
Having 32-bit virtual-address, 4 KB pages and 4 bytes/page of table entry, the total no of page-table size would be |
| A. | 1MB |
| B. | 2MB |
| C. | 3MB |
| D. | 4MB |
| Answer» E. | |
| 93. |
A queue holding data while the data are waiting to be written in memory, is known as |
| A. | Read buffer |
| B. | Queue buffer |
| C. | Write buffer |
| D. | Data buffer |
| Answer» D. Data buffer | |
| 94. |
Cache having 64 blocks and a block-size of 16 bytes, will have block-no for address 1200 map to |
| A. | 75 modulo 64 |
| B. | 75 modulo 60 |
| C. | 70 modulo 64 |
| D. | 72 modulo 64 |
| Answer» B. 75 modulo 60 | |
| 95. |
The spatial locality, is also known as |
| A. | Temporal locality |
| B. | Locality in space |
| C. | Locality in time |
| D. | Spectral Locality |
| Answer» C. Locality in time | |
| 96. |
In terms of the no of read accesses/program, the miss penalty in clock-cycles for a reading, and the reading miss-rate, is defined as |
| A. | Write-stall |
| B. | Queue buffer |
| C. | Write buffer |
| D. | Read-stall |
| Answer» E. | |
| 97. |
The main memory of a computer can act as a |
| A. | Virtual memory |
| B. | Main memory |
| C. | Cache |
| D. | Buffer |
| Answer» B. Main memory | |
| 98. |
Having a cache block of 4words, having one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be |
| A. | 0.2 |
| B. | 0.25 |
| C. | 0.75 |
| D. | 1.5 |
| Answer» C. 0.75 | |
| 99. |
The range of designs between direct-mapped and fully-associative cache, is called |
| A. | Set definitive |
| B. | Set associative |
| C. | Fully associative |
| D. | Block associative |
| Answer» C. Fully associative | |
| 100. |
If the entries no is a power of 2 in the cache, then modulo will be computed by using the |
| A. | Low-order log2 |
| B. | High-order log2 |
| C. | Low-order log10 |
| D. | High-order log10 |
| Answer» B. High-order log2 | |