MCQOPTIONS
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MCQOPTIONS
This section includes 373 Mcqs, each offering curated multiple-choice questions to sharpen your Technical Programming knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Operating System maintains the page table for ____________ |
| A. | each process |
| B. | each thread |
| C. | each instruction |
| D. | each address |
| Answer» B. each thread | |
| 2. |
The page table contains ____________ |
| A. | base address of each page in physical memory |
| B. | page offset |
| C. | page size |
| D. | none of the mentioned |
| Answer» B. page offset | |
| 3. |
Program always deals with ____________ |
| A. | logical address |
| B. | absolute address |
| C. | physical address |
| D. | relative address |
| Answer» B. absolute address | |
| 4. |
The address of a page table in memory is pointed by ____________ |
| A. | stack pointer |
| B. | page table base register |
| C. | page register |
| D. | program counter |
| Answer» C. page register | |
| 5. |
Run time mapping from virtual to physical address is done by ____________ |
| A. | Memory management unit |
| B. | CPU |
| C. | PCI |
| D. | None of the mentioned |
| Answer» B. CPU | |
| 6. |
A memory buffer used to accommodate a speed differential is called ____________ |
| A. | stack pointer |
| B. | cache |
| C. | accumulator |
| D. | disk buffer |
| Answer» C. accumulator | |
| 7. |
CPU fetches the instruction from memory according to the value of ____________ |
| A. | program counter |
| B. | status register |
| C. | instruction register |
| D. | program status word |
| Answer» B. status register | |
| 8. |
Where is String Pool stored? |
| A. | Java Stack |
| B. | Java Heap |
| C. | Permanent Generation |
| D. | Metaspace |
| Answer» C. Permanent Generation | |
| 9. |
Classes and Methods are stored in which space? |
| A. | Eden space |
| B. | Survivor space |
| C. | Tenured space |
| D. | Permanent space |
| Answer» E. | |
| 10. |
Which of the following is not a memory classification in java? |
| A. | Young |
| B. | Old |
| C. | Permanent |
| D. | Temporary |
| Answer» E. | |
| 11. |
Which class loader loads jar files from JDK directory? |
| A. | Bootstrap |
| B. | Extension |
| C. | System |
| D. | Heap |
| Answer» C. System | |
| 12. |
Which one of the following is a class loader? |
| A. | Bootstrap |
| B. | Compiler |
| C. | Heap |
| D. | Interpreter |
| Answer» B. Compiler | |
| 13. |
What is JVM? |
| A. | Bootstrap |
| B. | Interpreter |
| C. | Extension |
| D. | Compiler |
| Answer» C. Extension | |
| 14. |
Does code Segment loads the java code? |
| A. | True |
| B. | False |
| Answer» B. False | |
| 15. |
What is the access time of MCM51000AP10? |
| A. | 100ns |
| B. | 80ns |
| C. | 60ns |
| D. | 40ns |
| Answer» B. 80ns | |
| 16. |
Which memory package has a single row of pins? |
| A. | SIMM |
| B. | DIP |
| C. | SIP |
| D. | zig-zag |
| Answer» D. zig-zag | |
| 17. |
What is the required voltage of DIMM? |
| A. | 2V |
| B. | 2.2V |
| C. | 5V |
| D. | 3.3V |
| Answer» E. | |
| 18. |
Which is a subassembly package? |
| A. | dual-in-line |
| B. | zig-zag |
| C. | simm |
| D. | ceramic shell |
| Answer» D. ceramic shell | |
| 19. |
Which package has high memory speed and change in the supply? |
| A. | DIP |
| B. | SIMM |
| C. | DIMM |
| D. | zig-zag |
| Answer» D. zig-zag | |
| 20. |
Which of the following consist two lines of legs on both sides of a plastic or ceramic body? |
| A. | SIMM |
| B. | DIMM |
| C. | Zig-zag |
| D. | Dual in-line |
| Answer» E. | |
| 21. |
Which of the following technique is used by the UNIX operating system? |
| A. | logical address memory |
| B. | physical address memory |
| C. | virtual memory technique |
| D. | translational address |
| Answer» D. translational address | |
| 22. |
What can be done for the fine grain protection of the processor? |
| A. | add extra description bit |
| B. | add error signal |
| C. | add wait stage |
| D. | remains unchanged |
| Answer» B. add error signal | |
| 23. |
Which of the following is used by the M68000 family? |
| A. | M68000 |
| B. | 80386 |
| C. | 8086 |
| D. | 80286 |
| Answer» B. 80386 | |
| 24. |
Which of the following provides stability to the multitasking system? |
| A. | memory |
| B. | DRAM |
| C. | SRAM |
| D. | Memory partitioning |
| Answer» E. | |
| 25. |
What is the main purpose of the memory management unit? |
| A. | address translation |
| B. | large storage |
| C. | reduce the size |
| D. | provides address space |
| Answer» B. large storage | |
| 26. |
Which of the following is replaced with the absolute addressing mode? |
| A. | relative addressing mode |
| B. | protective addressing mode |
| C. | virtual addressing mode |
| D. | temporary addressing mode |
| Answer» B. protective addressing mode | |
| 27. |
How many numbers of ways are possible for allocating the memory to the modular blocks? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 28. |
Which of the following can destroy the accuracy in the algorithms? |
| A. | delays |
| B. | error signal |
| C. | interrupt |
| D. | mmu |
| Answer» B. error signal | |
| 29. |
Which of the following have a 16 Mbytes addressed range? |
| A. | PowerPC |
| B. | M68000 |
| C. | DSP56000 |
| D. | TMS 320 |
| Answer» C. DSP56000 | |
| 30. |
Data storage in a memory is termed as |
| A. | memorizing |
| B. | reading |
| C. | writing |
| D. | loading |
| Answer» D. loading | |
| 31. |
Assume that a 16 bit CPU is trying to access a double word starting at an odd address. How many memory operations are required to access the data? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 32. |
_______ is a form of permanent memory that holds all the instructions the computer needs to start up does not get erased when the power is turned off. |
| A. | The network Interface Card (NIC) |
| B. | The CPU |
| C. | RAM |
| D. | ROM |
| E. | None of these |
| Answer» E. None of these | |
| 33. |
If main memory access time is 400 μs, TLB access time is 50 μs, considering TLB hit as 90%, what will be the overall access time? |
| A. | 800 μs |
| B. | 490 μs |
| C. | 485 μs |
| D. | 450 μs |
| Answer» C. 485 μs | |
| 34. |
How many 128 × 8 bit RAMs are required to design 32K × 32 bit RAM? |
| A. | 512 |
| B. | 1024 |
| C. | 128 |
| D. | 32 |
| Answer» C. 128 | |
| 35. |
Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache, and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache? |
| A. | 13.0 ns |
| B. | 12.8 ns |
| C. | 12.6 ns |
| D. | 12.4 ns |
| Answer» D. 12.4 ns | |
| 36. |
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880Which one of the following is TRUE? |
| A. | A1 and A4 are mapped to different cache sets. |
| B. | A2 and A3 are mapped to the same cache set. |
| C. | A3 and A4 are mapped to the same cache set. |
| D. | A1 and A3 are mapped to the same cache set. |
| Answer» C. A3 and A4 are mapped to the same cache set. | |
| 37. |
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.Which of the following statements is correct? |
| A. | S1 is true and S2 is true |
| B. | S1 is false and S2 is true |
| C. | S1 is false and S2 is false |
| D. | S1 is true and S2 is false |
| Answer» E. | |
| 38. |
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)? |
| A. | 60 ns |
| B. | 30 ns |
| C. | 150 ns |
| D. | 70 ns |
| Answer» B. 30 ns | |
| 39. |
CD-R stands for ______and can be written to only______ . |
| A. | Compact Disc - Recordable; once |
| B. | Concurrent Disc - Recordable; once |
| C. | Compact Disc - Recordable; twice |
| D. | Concurrent Disc - Recordable; twice |
| Answer» B. Concurrent Disc - Recordable; once | |
| 40. |
Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): A memory module presents a specific memory interface to the processor or other unit that references memory.Reason (R): The memory module contains buffer registers for the address and data. |
| A. | Both A and R are individually true and R is the correct explanation of A |
| B. | Both A and R are individually true but R is NOT the correct explanation of A |
| C. | A is true but R is false |
| D. | A is false but R is true |
| Answer» B. Both A and R are individually true but R is NOT the correct explanation of A | |
| 41. |
Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines used with this machine. How many bits will be there in Tag. line and word field of format of main memory addresses ? |
| A. | 8, 5, 3 |
| B. | 8, 6, 2 |
| C. | 7, 5, 4 |
| D. | 7, 6, 3 |
| Answer» B. 8, 6, 2 | |
| 42. |
A CPU has a 32 KB direct mapped cache with 128 byte block size. Suppose A is a 2 dimensional array of size 512*512 with elements that occupy 8 bytes each. Consider the code segmentfor (i =0; i < 512; i++) {for (j =0; j < 512; j++) {x += A[i][j];}}Assuming that array is stored in order A[0][0], A[0][1], A[0][2]……, the number of cache misses is |
| A. | 16384 |
| B. | 512 |
| C. | 2048 |
| D. | 1024 |
| Answer» B. 512 | |
| 43. |
Directions: The question consists of two statements, one labeled as ‘Statement (I)’ and the other labeled as ‘Statement (II)’. You are to examine these two statements carefully and select the answers to these items using the codes given below:Statement (I): A buffer is not an area in RAM or on the hard drive designated to hold input and output on their way in or out of the system.Statement (II): The process of placing items in a buffer so they can be retrieved by the appropriate device when needed is called spooling. |
| A. | Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I). |
| B. | Both Statement (I) and Statement (II) are individually true, but Statement (II) is not the correct explanation of Statement (I). |
| C. | Statement (I) is true, but Statement (II) is false. |
| D. | Statement (I) is false, but Statement (II) is true. |
| Answer» E. | |
| 44. |
In a two-level cache system, the access times of L1 and L2 caches are 1 and 8 clock cycles, respectively. The miss penalty from the L2 cache to main memory is 18 clock cycles. The miss rate of L1 cache is twice that of L2. The average memory access time (AMAT) of this cache system is 2 cycle. The miss rates of L1 and L2 respectively are: |
| A. | 0.111 and 0.056 |
| B. | 0.056 and 0.111 |
| C. | 0.0892 and 0.1784 |
| D. | 0.1784 and 0.0892 |
| Answer» B. 0.056 and 0.111 | |
| 45. |
An 8085-microprocessor based system uses a 4K × 8 bit RAM whose starting address is AA00H. The address of the last byte in this RAM is: |
| A. | 0FFFH |
| B. | 1000H |
| C. | B9FFH |
| D. | BA00H |
| Answer» D. BA00H | |
| 46. |
A CPU's processing power is measured in |
| A. | IPS |
| B. | CIPS |
| C. | MIPS |
| D. | nano-seconds |
| Answer» D. nano-seconds | |
| 47. |
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 × 6 array, where each chip is 8K × 4 bits? |
| A. | 13 |
| B. | 15 |
| C. | 16 |
| D. | 17 |
| Answer» E. | |
| 48. |
In a three level memory hierarchy, the access time of cache, main and virtual memory is 5 nano-seconds, 100 nano-seconds and 10 milli-seconds respectively. If the hit ratio is 80% for the cache and 99.5% for the main memory, then the closest average access time of memory hierarchy in nano-seconds is: |
| A. | 512 |
| B. | 1024 |
| C. | 10024 |
| D. | 128 |
| Answer» D. 128 | |
| 49. |
A computer has 1000K of main memory. The jobs arrive and finish in the following sequence.Job 1 requiring 200 K arrivesJob 2 requiring 350 K arrivesJob 3 requiring 300 K arrivesJob 1 finishesJob 4 requiring 120 K arrivesJob 5 requiring 150 K arrivesJob 6 requiring 80 K arrivesAmong best fit and first fit, which performs better for this sequence? |
| A. | First fit |
| B. | Best fit |
| C. | Both perform the same |
| D. | None of the above |
| Answer» B. Best fit | |
| 50. |
In microprocessor terminology, what does DMA stand for? |
| A. | Direct Memory Advice |
| B. | Direct Memory Access |
| C. | Dual Memory Access |
| D. | Direct Memorable Access |
| Answer» C. Dual Memory Access | |