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MCQOPTIONS
This section includes 373 Mcqs, each offering curated multiple-choice questions to sharpen your Technical Programming knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
In the year 1993, _________ introduced the first microcontroller using flash memory. |
| A. | Atmel |
| B. | Intel |
| C. | Alchemist |
| D. | Ericson |
| Answer» B. Intel | |
| 102. |
How many binary numbers are created with 8 bits? |
| A. | 64 |
| B. | 16 |
| C. | 128 |
| D. | 256 |
| Answer» E. | |
| 103. |
A disk unit has 24 recording surfaces. It has a total of 14000 cylinders. There is an average of 400 sectors per track. Each sector contains 512 bytes of data. What is the data transfer rate at a rotational speed of 7200 r.p.m? |
| A. | 68.80 × 106 bytes/s |
| B. | 24.58 × 106 bytes/s |
| C. | 98.80 × 103 bytes/s |
| D. | 24.58 × 103 bytes/s |
| Answer» C. 98.80 × 103 bytes/s | |
| 104. |
An example for magnetic storage device is: |
| A. | OMR |
| B. | Hard Disk |
| C. | CD-ROM disc |
| D. | Memory Strip |
| Answer» C. CD-ROM disc | |
| 105. |
If the disk platters rotate at 5400 rpm (revolutions per minute), then approximately what is the maximum rotational delay ? |
| A. | 0.011 seconds |
| B. | 0.11 seconds |
| C. | 0.0011 seconds |
| D. | 1.1 seconds |
| Answer» B. 0.11 seconds | |
| 106. |
A soft-error is a |
| A. | regular non-destructive event |
| B. | random non-destructive event |
| C. | random destructive event |
| D. | regular destructive event |
| Answer» C. random destructive event | |
| 107. |
Data transfer between the main memory and the CPU register takes place through two registers, namely, |
| A. | General purpose register and MDR |
| B. | Accumulator and Program counter |
| C. | MAR and MDR |
| D. | MAR and Accumulator |
| Answer» D. MAR and Accumulator | |
| 108. |
A cache line has 128 bytes. The main memory has latency 64 ns and bandwidth 1 GB/s. The time required to fetch the entire cache line is |
| A. | 32 ns |
| B. | 64 ns |
| C. | 96 ns |
| D. | 192 ns |
| Answer» E. | |
| 109. |
Consider the following sizes of computer memory. Choose the correct ascending orderA. MBB. GBC. KBD. TBChoose the correct answer from the options given below |
| A. | B, D, A, C |
| B. | D, B, A, C |
| C. | A, B, C, D |
| D. | C, A, B D |
| Answer» E. | |
| 110. |
A computer employs RAM chips of 256 bytes and ROM chips of 1024 bytes. If the computer system needs 1kB of RAM and 1kB of ROM, then how many address lines are required to access the memory? |
| A. | 10 |
| B. | 11 |
| C. | 12 |
| D. | 13 |
| Answer» C. 12 | |
| 111. |
Aliasing in the context of programming language refers to multiple variables having the same: |
| A. | memory location |
| B. | value |
| C. | identifier |
| D. | none of these |
| Answer» B. value | |
| 112. |
A programmed stored in a higher memory that can be used repeatedly as part of main program is known as |
| A. | sub program |
| B. | micro program |
| C. | sub routine |
| D. | library |
| Answer» E. | |
| 113. |
A byte is group of: |
| A. | 2 bits |
| B. | 4 bits |
| C. | 8 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 114. |
A computer system has a cache with access time 10 ns, a hit ratio of 80% and average memory access time is 20 ns. Then what is the access time for physical memory? |
| A. | 50 ns |
| B. | 40 ns |
| C. | 30 ns |
| D. | 20 ns |
| Answer» B. 40 ns | |
| 115. |
In context of a magnetic disk time taken to move the read/write head on to desired track is called _____ time and time taken for desired sector track to come under read/write head is called _____ |
| A. | Seek, Latency |
| B. | Latency, Seek |
| C. | Access, Latency |
| D. | Access, Seek |
| Answer» B. Latency, Seek | |
| 116. |
If one track of data can be transferred per revolution, then what is the data transfer rate ? |
| A. | 2,850 KBytes/second |
| B. | 4,500 KBytes/second |
| C. | 5,700 KBytes/second |
| D. | 2,250 KBytes/second |
| Answer» E. | |
| 117. |
Protecting data by copying it from the original source to a diifferent destination is called |
| A. | Formatting |
| B. | Hacking |
| C. | Backup |
| D. | Data diddling |
| E. | None of these |
| Answer» D. Data diddling | |
| 118. |
Like EPROM, flash memory uses only ______ transistor(s) per bit, and so achieves the high density (compared with EEPROM) of EPROM. |
| A. | one |
| B. | two |
| C. | three |
| D. | four |
| Answer» B. two | |
| 119. |
Computational circuitry in a CPU is referred to as the ____________ |
| A. | ALU |
| B. | Program Counter |
| C. | ROM |
| D. | RAM |
| Answer» B. Program Counter | |
| 120. |
How many total bits are required for a direct-mapped cache with 128 KB of data and 1 word block size, assuming a 32-bit address and 1 word size of 4 bytes? |
| A. | 2 Mbits |
| B. | 1.7 Mbits |
| C. | 2.5 Mbits |
| D. | 1.5 Mbits |
| Answer» E. | |
| 121. |
Main memory is also called as |
| A. | ROM |
| B. | Hard Disk |
| C. | RAM |
| D. | PROM |
| Answer» D. PROM | |
| 122. |
Consider that a level of the memory hierarchy has a hit rate of 80%. Memory requests take 10 ns to complete if they hit in the level, and memory requests that miss in the level take 100 ns to complete. The average access time of the level is |
| A. | 110 ns |
| B. | 100 ns |
| C. | 80 ns |
| D. | 28 ns |
| Answer» E. | |
| 123. |
It is required to refresh _________ after a certain time interval. |
| A. | State RAM |
| B. | Dynamic RAM |
| C. | Magnetic Memory |
| D. | Optical Memory |
| Answer» C. Magnetic Memory | |
| 124. |
Consider six memory partitions of sizes 200 KB, 400 KB, 600 KB, 500 KB, 300 KB and 250 KB, where KB refers to kilobyte. These partitions need to be allotted to four processes of sizes 357 KB, 210 KB, 468 KB and 491 KB in that order. If the best fit algorithm is used, which partitions are NOT allotted to any process? |
| A. | 200 KB and 300 KB |
| B. | 200 KB and 250 KB |
| C. | 250 KB and 300 KB |
| D. | 300 KB and 400 KB |
| Answer» B. 200 KB and 250 KB | |
| 125. |
______ is the fastest to read from and write to than the other kinds of storage in a computer. |
| A. | Floppy disk |
| B. | Hard disk |
| C. | CD-ROM |
| D. | RAM |
| Answer» E. | |
| 126. |
Assuming that packet transmissions and retransmission can both be described as a Poisson process, calculate the probability that a data packet transmission in an S-ALOHA system will experience a collision with another user. Assume the total traffic rate λt = 10 packets/sec and the packet duration τ = 10 msec. |
| A. | 0.9 |
| B. | 0.09 |
| C. | 0.009 |
| D. | 9.0 |
| Answer» C. 0.009 | |
| 127. |
A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» D. 16 | |
| 128. |
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? |
| A. | 24 bits and 0 bits |
| B. | 28 bits and 4 bits |
| C. | 24 bits and 4 bits |
| D. | 28 bits and 0 bits |
| Answer» E. | |
| 129. |
A computer uses RAM chips of 1024 × 1 capacity.How many chips are needed to provide memory capacity of 16K bytes? |
| A. | 8 |
| B. | 16 |
| C. | 1024 |
| D. | 128 |
| Answer» E. | |
| 130. |
A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» D. 16 | |
| 131. |
Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss? |
| A. | 16 × 2010 |
| B. | 256 × 210 |
| C. | 4 × 220 |
| D. | 8 × 220 |
| Answer» C. 4 × 220 | |
| 132. |
One-megabyte memory storage in form of bytes is equal to _____. |
| A. | 1024 bytes |
| B. | 10242 bytes |
| C. | 10243 bytes |
| D. | 10244 bytes |
| Answer» C. 10243 bytes | |
| 133. |
In computers, some area in the memory is reserved for high speed operations and storing frequently used instructions. What is the name of this type of memory? |
| A. | Flash |
| B. | Cache |
| C. | SRAM |
| D. | Northbridge |
| Answer» C. SRAM | |
| 134. |
In a DMA write operation the data is transferred |
| A. | from I/ O to memory |
| B. | from memory to I/ O |
| C. | from memory to memory |
| D. | from I/ O to I/ O |
| Answer» B. from memory to I/ O | |
| 135. |
If ‘m’ is the number of bits in a memory address and ‘n’ is the number of addressable units, then which of the following represents the correct relationship between ‘m’ and ‘n’? |
| A. | n = 2m |
| B. | m = 2n |
| C. | m = 2n - 1 |
| D. | n = 2m + 1 |
| Answer» B. m = 2n | |
| 136. |
________ refers to the amount of time required to position the read - white head of a hard disk on appropriate sector. |
| A. | Seek time |
| B. | Rotational latency |
| C. | Access time |
| D. | Load time |
| Answer» B. Rotational latency | |
| 137. |
Principle of locality is used in _______. |
| A. | Registers |
| B. | DMA |
| C. | Cache Memory |
| D. | Interrupt |
| Answer» D. Interrupt | |
| 138. |
Cache and main memory will not be able to hold their contents when the power is off. They are |
| A. | Dynamic |
| B. | Static |
| C. | Volatile |
| D. | Non – volatile |
| E. | Faulty |
| Answer» D. Non – volatile | |
| 139. |
Choose the smallest memory size unit. |
| A. | KB |
| B. | MB |
| C. | GB |
| D. | TB |
| Answer» B. MB | |
| 140. |
Print quality of printer is given in _________ and printing speed is given in _________. |
| A. | Paper Per Minute (PPM), Dot Per Inch (DPI) |
| B. | Chromatic Number (CN), Rotation Per Minute (RPM) |
| C. | Dot Per Inch (DPI), Paper Per Minute (PPM) |
| D. | Dot Per Inch (DPI), Rotation Per Minute (RPM) |
| Answer» D. Dot Per Inch (DPI), Rotation Per Minute (RPM) | |
| 141. |
Flash memory is made up of |
| A. | RDRAM |
| B. | MROM |
| C. | SRAM |
| D. | EEPROM |
| E. | PROM |
| Answer» E. PROM | |
| 142. |
If there are 32 segments, each size 1 k bytes, then the logical address should have |
| A. | 13 bits |
| B. | 14 bits |
| C. | 15 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 143. |
If a symbol is erased from a memory cell as a consequence of reading, then the readout is said to be |
| A. | Non-volatile |
| B. | Volatile |
| C. | Destructive |
| D. | Non-destructive |
| Answer» D. Non-destructive | |
| 144. |
A direct mapped cache is of size 32 KB and has block size 32 Bytes. CPU also generates 32 bit address. Number of bits needed for indexing the cache: |
| A. | 14 |
| B. | 15 |
| C. | 10 |
| D. | 17 |
| Answer» D. 17 | |
| 145. |
Given below are two statements:Statement I: The disk has a total number of 2000 cylinders.Statement II: 51200 bytes is not a valid block size for the disk.In the light of the above statements, choose the correct answer from the options given below: |
| A. | Both Statement I and Statement II are true |
| B. | Both Statement I and Statement II are false |
| C. | Statement I is correct but Statement II is false |
| D. | Statement I is incorrect but Statement II is true |
| Answer» B. Both Statement I and Statement II are false | |
| 146. |
Dynamic RAM consumes_______ Power and is _______ than Static RAM |
| A. | More, Faster |
| B. | More, Slower |
| C. | Less, Slower |
| D. | Less, Faster |
| Answer» D. Less, Faster | |
| 147. |
A two way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The physical address space is 4 GB. The number of bits in the TAG, SET fields are |
| A. | 20, 7 |
| B. | 19, 8 |
| C. | 20, 8 |
| D. | 21, 9 |
| Answer» C. 20, 8 | |
| 148. |
Permanent Memory of a computer is known as- |
| A. | RAM |
| B. | CD-ROM |
| C. | ROM |
| D. | CPU |
| Answer» D. CPU | |
| 149. |
In a computer when the access time taken is less, the speed of the memory is ______. |
| A. | Faster |
| B. | Inconsistent |
| C. | Slower |
| D. | Constant |
| Answer» B. Inconsistent | |
| 150. |
In a computer system, memory mapped access takes 100 nanoseconds when a page is found in TLB. In case the page is not TLB, it takes 400 nanoseconds to access. Assuming a hit ratio of 80%, the effective access time is: |
| A. | 120ns |
| B. | 160ns |
| C. | 200ns |
| D. | 500ns |
| Answer» C. 200ns | |