The device shown in the given figure is checked with a logic probe and the output is HIGH.

The device is working properly.

For the input conditions shown the output should be LOW; the input is shorted to ground.

For the input conditions shown the output should be neither HIGH nor LOW; the device is shorted to

The device is probably alright; the problem is most likely caused by the stage connected to the output of the device.

Refer the given figure. The outputs (Q0–Q3) of the memory are always LOW. The address lines (A0–A7) are checked with a logic probe and all are indicating pulse activity, except for A3, which shows a constant HIGH, and A7, which shows a constant LOW; the select lines, are checked and shows pulse activity, while indicates a constant HIGH. What is wrong, and how can the memory be tested to determine whether it is defective or if the external circuitry is defective?

The problem appears to be in the two address lines that never change levels; the problem is probably in the program driving the memory address bus.

One of the inputs to the active-LOW select AND gate may be stuck high for some reason; take both select lines LOW and check for pulse activity on the outputs, Q0–Q3. If the outputs now respond, the problem is most likely in the program or circuitry driving the select lines.

The problem appears to be in the two address lines that never change levels; the problem is probably in the program driving the memory address bus.

The output buffers are probably defective since they are all tied together; the common input line is most likely stuck LOW. Change the output buffer IC.

Since no data appears to be getting through to the output buffers, the problem may be in the X decoder; change the X decoder IC.

ROM access time is defined as ________.

the time required to activate the address lines after the ENABLE line is at a valid level

how long it takes to program the ROM chip

being the difference between the READ and WRITE times

the time it takes to get valid output data after a valid address is applied

the time required to activate the address lines after the ENABLE line is at a valid level

204 + Mcqs in Memory And Storage in Digital Electronics Page 1 McqOptions

1.	Because 4096 = 2, a 4K × 1 RAM requires ________ address bits to access all locations.
A.	4096
B.	10
C.	12
D.	1024
Answer» D. 1024

2.	The time delay called access time, , is a measure of the ROM's operating speed.
A.	True
B.	False
Answer» C.

3.	RAMs must have a input, in addition to data in.
A.	True
B.	False
Answer» B. False

5.	What are the typical values of ?
A.	10 to 20 ns for bipolar
B.	25 to 100 ns for NMOS
C.	12 to 50 ns for CMOS
D.	All of the above
Answer» E.

6.	The time from the beginning of a read cycle to the end of or is referred to as:
A.	access time
B.	data hold
C.	read cycle time
D.	write enable time
Answer» B. data hold

7.	The number of 16k × 4 memories needed to construct a 128k × 8 memory is ________.
A.	4
B.	8
C.	12
D.	16
Answer» E.

8.	How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
A.	Eight
B.	Four
C.	Two
D.	One
Answer» B. Four

9.	How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?
A.	2
B.	4
C.	8
D.	9
Answer» E.

10.	What is the bit storage capacity of a ROM with a 1024 × 8 organization?
A.	1024
B.	2048
C.	4096
D.	8192
Answer» E.

11.	The address-decoding scheme for a 16K-byte EPROM memory system requires a 1-to-8-address decoder when 4K × 8 memory is used.
A.	True
B.	False
Answer» B. False

12.	How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?
A.	2
B.	4
C.	8
D.	16
Answer» D. 16

15.	The 2147 4K × 1 static RAM contains 4096 storage locations storing one bit each. ________ 2147 RAM memory chip(s) is/are needed to configure an 8K × 8 memory.
A.	One
B.	Four
C.	Eight
D.	Sixteen
Answer» E.

20.	Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?
A.	8,000
B.	64,000
C.	65,536
D.	8,192
Answer» E.

21.	Most flash chips use a bulk erase operation in which all cells on the chip are erased simultaneously.
A.	1
B.
Answer» B.

22.	A term often used commercially to refer to read/write memory is sequential-access memory.
A.	1
B.
Answer» C.

13.	How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?
A.	2
B.	4
C.	8
D.	16
Answer» B. 4

14.	How many address lines would be required for a 2K × 4 memory chip?
A.	8
B.	10
C.	11
D.	12
Answer» D. 12

16.	Because 4096 = 212, a 4K × 1 RAM requires ________ address bits to access all locations.
A.	4096
B.	10
C.	12
D.	1024
Answer» D. 1024

17.	The TMS44100 4M × 1 DRAM does not have a chip select (SC) input.
A.	True
B.	False
Answer» B. False

18.	Dynamic memories, such as the 2118 16K × 1 RAM, have to multiplex the address bus.
A.	True
B.	False
Answer» B. False

23.	Because 4096 = 212, a 4K √ó 1 RAM requires ________ address bits to access all locations.
A.	4096
B.	10
C.	12
D.	1024
Answer» D. 1024

24.	Erasing or programming a flash memory device is a one-step operation.
A.	1
B.
Answer» C.

25.	A(n) ________ is user programmable and can also be erased electronically and reprogrammed as often as desired.
A.	PROM
B.	ROM
C.	EEPROM
D.	EPROM
Answer» D. EPROM

28.	A type of read/write memory available with MOS technology is ________.
A.	SRAM
B.	DRAM
C.	both of the above
D.	none of the above
Answer» D. none of the above

29.	When two or more devices try to send their own digital levels to a shared data bus at the same time, bus contention will take place.
A.	1
B.
Answer» B.

Explore topic-wise MCQs in Digital Electronics.

Because 4096 = 2, a 4K × 1 RAM requires ________ address bits to access all locations.

The time delay called access time, , is a measure of the ROM's operating speed.

RAMs must have a input, in addition to data in.

The device shown in the given figure is checked with a logic probe and the output is HIGH.

What are the typical values of ?

The time from the beginning of a read cycle to the end of or is referred to as:

The number of 16k × 4 memories needed to construct a 128k × 8 memory is ________.

How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?

How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?

What is the bit storage capacity of a ROM with a 1024 × 8 organization?

The address-decoding scheme for a 16K-byte EPROM memory system requires a 1-to-8-address decoder when 4K × 8 memory is used.

How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?

How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?

How many address lines would be required for a 2K × 4 memory chip?

The 2147 4K × 1 static RAM contains 4096 storage locations storing one bit each. ________ 2147 RAM memory chip(s) is/are needed to configure an 8K × 8 memory.

Because 4096 = 212, a 4K × 1 RAM requires ________ address bits to access all locations.

The TMS44100 4M × 1 DRAM does not have a chip select (SC) input.

Dynamic memories, such as the 2118 16K × 1 RAM, have to multiplex the address bus.

Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?

Most flash chips use a bulk erase operation in which all cells on the chip are erased simultaneously.

A term often used commercially to refer to read/write memory is sequential-access memory.

Because 4096 = 212, a 4K √ó 1 RAM requires ________ address bits to access all locations.

Erasing or programming a flash memory device is a one-step operation.

A(n) ________ is user programmable and can also be erased electronically and reprogrammed as often as desired.

The address-decoding scheme for a 16K-byte EPROM memory system requires a 1-to-8-address decoder when 4K √ó 8 memory is used.

The time from the beginning of a read cycle to the point when the data output is valid is called propagation delay.

A type of read/write memory available with MOS technology is ________.

When two or more devices try to send their own digital levels to a shared data bus at the same time, bus contention will take place.

Flash memories are so called because of the rapid ________ times.

An optical disk is an example of magnetic storage.

ROMs are used to store data on a permanent basis.

The major advantage of dynamic RAM over static RAM is ________.

Main computer memory is usually DRAM because of its high density and low cost; cache memory is usually SRAM because of its high speed.

ROM access time is defined as ________.

The time delay called access time, tac, is a measure of the ROM's operating speed.

The 2147 4K √ó 1 static RAM contains 4096 storage locations storing one bit each. ________ 2147 RAM memory chip(s) is/are needed to configure an 8K √ó 8 memory.

EEPROMS can be electrically erased and reused.

DRAM chips can be combined for larger capacity and word sizes using the same methods as for other memory types.

A ________ is user-programmable memory that cannot be erased and reprogrammed.

The floating-gate MOSFET is the actual storage element for EEPROMs. An electron charge will remain on the floating gate for more than 10 years unless drained off electrically.

A typical RAM will write (store data internally) whenever the Chip Select line is active and the Write Enable line is inactive.

A ROM that allows the user to program data into the chip by permanently opening fusible links is the EPROM.

A group of 6 bits is also known as 1 byte.

When a computer is executing a program of instructions, the CPU will ________ memory locations as dictated by the program instructions.

In a register stack, data moves up but not down.

Cache memory is used in high-speed systems.

DRAM uses a cross-transistor configuration.

In DRAM operations, it is assumed that R/W is in its ________ state during a ________ operation.

The minimum number of address lines needed for a 64K memory is ________.

In DRAM operations, it is assumed that R/W is in its state during a operation.

30.	Flash memories are so called because of the rapid ________ times.
A.	read and write
B.	format and erase
C.	erase and read
D.	erase and write
Answer» E.

33.	The major advantage of dynamic RAM over static RAM is ________.
A.	cost
B.	speed
C.	storage density
D.	cost and storage density
Answer» E.

45.	When a computer is executing a program of instructions, the CPU will ________ memory locations as dictated by the program instructions.
A.	format
B.	scan
C.	store data into
D.	verify
Answer» D. verify

49.	In DRAM operations, it is assumed that R/W is in its ________ state during a ________ operation.
A.	HIGH, read
B.	Hi-Z, write
C.	HIGH, write
D.	Hi-Z, read
Answer» B. Hi-Z, write