Interconnect capacitance is formed due to ___________

Junction capacitance between gate and substrate

Wire connecting the gates of 2 different inverters

Parasitic capacitance existing between metal and polysilicon connection between 2 inverters

The load capacitance is equivalent to ___________

Sum of all junction capacitance between Vcc and ground

Sum of all lumped linear capacitances between input and output node

Sum of all junction capacitance between Vcc and ground

Sum of all junction capacitance between input and output

Sum of all lumped linear capacitances between output node and ground

In the below graph, the regions marked as A,B,C are?

A : Linear, B : Saturation, C : Cut-off

A : Saturation, B : Linear, C : Cut-off

A :Cut-off, B : Linear, C : Saturation

A : Linear, B : Saturation, C : Cut-off

In saturation mode operation, gate to drain capacitance is zero due to ___________

Inversion layer doesn’t exist

Gate and drain are interconnected

Inversion layer doesn’t exist

In linear mode operation, the parasitic capacitances that exists are ___________

Nonzero Gate to source capacitance

Nonzero Gate to drain capacitance

Zero gate to substrate capacitance

The capacitances in MOSFET occurs due to _____________

Difference in Doping concentration

Interconnect capacitance is formed due to:

Junction capacitance between gate and substrate

Wire connecting the gates of 2 different inverters

Parasitic capacitance existing between metal and polysilicon connection between 2 inverters

The load capacitance is equivalent to:

Sum of all junction capacitance between Vcc and ground

Sum of all lumped linear capacitances between input and output node

Sum of all junction capacitance between Vcc and ground

Sum of all junction capacitance between input and output

Sum of all lumped linear capacitances between output node and ground

In saturation mode operation, gate to drain capacitance is zero due to?

Inversion layer doesn‚Äö√Ñ√∂‚àö√ë‚àö¬•t exit

Gate and drain are interconnected

Inversion layer doesn‚Äö√Ñ√∂‚àö√ë‚àö¬•t exit

Nonzero Gate to source capacitance

Nonzero Gate to drain capacitance

Zero gate to substrate capacitance

The capacitances in MOSFET occurs due to:

Difference in Doping concentration

24 + Mcqs in Load Wiring Capacitance in Vlsi Page 1 McqOptions

1.	Which of the following parameters are found using load capacitance?
A.	Delay time
B.	Power consumption
C.	Speed of the CMOS logic
D.	All of the mentioned
Answer» E.

Discussion

2.	Interconnect capacitance is formed due to ___________
A.	Junction capacitance between gate and substrate
B.	Wire connecting the gates of 2 different inverters
C.	Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
D.	All of the mentioned
Answer» D. All of the mentioned

Discussion

3.	Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration.
A.	True
B.	False
Answer» B. False

Discussion

4.	The load capacitance is equivalent to ___________
A.	Sum of all lumped linear capacitances between input and output node
B.	Sum of all junction capacitance between Vcc and ground
C.	Sum of all junction capacitance between input and output
D.	Sum of all lumped linear capacitances between output node and ground
Answer» B. Sum of all junction capacitance between Vcc and ground

Discussion

5.	The load capacitance is measured between ___________
A.	Output node and input node
B.	Output node and Vcc
C.	Output node and ground
D.	Input node and ground
Answer» D. Input node and ground

Discussion

6.	In the below graph, the regions marked as A,B,C are?
A.	A : Saturation, B : Linear, C : Cut-off
B.	A :Cut-off, B : Linear, C : Saturation
C.	A : Linear, B : Saturation, C : Cut-off
D.	None of the mentioned
Answer» C. A : Linear, B : Saturation, C : Cut-off

Discussion

7.	When MOSFET is operating in saturation region, the gate to source capacitance is?
A.	1/2CoxW*L
B.	2/3CoxW*L
C.	CoxWL
D.	1/3CoxW*L
Answer» C. CoxWL

Discussion

8.	In saturation mode operation, gate to drain capacitance is zero due to ___________
A.	Gate and drain are interconnected
B.	Channel length is reduced
C.	Inversion layer doesn’t exist
D.	Drain is connected to ground
Answer» C. Inversion layer doesn’t exist

Discussion

9.	In linear mode operation, the parasitic capacitances that exists are ___________
A.	Nonzero Gate to source capacitance
B.	Nonzero Gate to drain capacitance
C.	Zero gate to substrate capacitance
D.	All of the mentioned
Answer» E.

Discussion

10.	In cut-off mode, the value of gate to substrate capacitance is equal to ___________
A.	Cox .(W- L)
B.	Cox W/ L
C.	Cox* W*L
D.	0
Answer» D. 0

Discussion

11.	In Cut-off Mode, the capacitance Cgs will be equal to ___________
A.	2Cgd
B.	0
C.	Cgb
D.	All of the mentioned
Answer» C. Cgb

Discussion

12.	The capacitance that exist between Gate and Bulk is called as ___________
A.	Oxide parasitic capacitance
B.	Metal oxide capacitance
C.	MOS capacitance
D.	None of the mentioned
Answer» B. Metal oxide capacitance

Discussion

13.	The parasitic capacitances found in MOSFET are ___________
A.	Oxide related capacitances
B.	Inter electrode capacitance
C.	Electrolytic capacitance
D.	All of the mentioned
Answer» B. Inter electrode capacitance

Discussion

14.	The capacitances in MOSFET occurs due to _____________
A.	Interconnects
B.	Difference in Doping concentration
C.	Difference in dopant materials
D.	All of the mentioned
Answer» E.

Discussion

15.	WHEN_MOSFET_IS_OPERATING_IN_SATURATION_REGION,_THE_GATE_TO_SOURCE_CAPACITANCE_IS_:?$
A.	1/2CoxW*L
B.	2/3CoxW*L
C.	CoxWL
D.	1/3CoxW*L
Answer» C. CoxWL

Discussion

16.	Interconnect capacitance is formed due to:
A.	Junction capacitance between gate and substrate
B.	Wire connecting the gates of 2 different inverters
C.	Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
D.	All of the mentioned
Answer» E.

Discussion

17.	The load capacitance is equivalent to:
A.	Sum of all lumped linear capacitances between input and output node
B.	Sum of all junction capacitance between Vcc and ground
C.	Sum of all junction capacitance between input and output
D.	Sum of all lumped linear capacitances between output node and ground
Answer» B. Sum of all junction capacitance between Vcc and ground

Discussion

18.	In saturation mode operation, gate to drain capacitance is zero due to?
A.	Gate and drain are interconnected
B.	Channel length is reduced
C.	Inversion layer doesn‚Äö√Ñ√∂‚àö√ë‚àö¬•t exit
D.	Drain is connected to ground
Answer» C. Inversion layer doesn‚Äö√Ñ√∂‚àö√ë‚àö¬•t exit

Discussion

19.	Nonzero Gate to source capacitance
A.	Nonzero Gate to drain capacitance
B.	Zero gate to substrate capacitance
C.	All of the mentioned
Answer» C. All of the mentioned

Discussion

20.	In cut-off mode, the value of gate to substrate capacitance is equal to:
A.	Cox .(W- L)
B.	Cox W/ L
C.	Cox* W*L
D.	0
Answer» D. 0

Discussion

21.	In Cut-off Mode, the capacitance Cgs will be equal to:
A.	2Cgd
B.	0
C.	Cgb
D.	All of the mentioned
Answer» C. Cgb

Discussion

22.	The capacitance that exist between Gate and Bulk is called as:
A.	Oxide parasitic capacitance
B.	Metal oxide capacitance
C.	MOS capacitance
D.	None of the mentioned
Answer» B. Metal oxide capacitance

Discussion

23.	The parasitic capacitances found in MOSFET are:
A.	Oxide related capacitances
B.	Inter electrode capacitance
C.	Electrolytic capacitance
D.	All of the mentioned
Answer» B. Inter electrode capacitance

Discussion

24.	The capacitances in MOSFET occurs due to:
A.	Interconnects
B.	Difference in Doping concentration
C.	Difference in dopant materials
D.	All of the mentioned
Answer» E.

Discussion

Explore topic-wise MCQs in Vlsi.

Which of the following parameters are found using load capacitance?

Interconnect capacitance is formed due to ___________

Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration.

The load capacitance is equivalent to ___________

The load capacitance is measured between ___________

In the below graph, the regions marked as A,B,C are?

When MOSFET is operating in saturation region, the gate to source capacitance is?

In saturation mode operation, gate to drain capacitance is zero due to ___________

In linear mode operation, the parasitic capacitances that exists are ___________

In cut-off mode, the value of gate to substrate capacitance is equal to ___________

In Cut-off Mode, the capacitance Cgs will be equal to ___________

The capacitance that exist between Gate and Bulk is called as ___________

The parasitic capacitances found in MOSFET are ___________

The capacitances in MOSFET occurs due to _____________

WHEN_MOSFET_IS_OPERATING_IN_SATURATION_REGION,_THE_GATE_TO_SOURCE_CAPACITANCE_IS_:?$

Interconnect capacitance is formed due to:

The load capacitance is equivalent to:

In saturation mode operation, gate to drain capacitance is zero due to?

Nonzero Gate to source capacitance

In cut-off mode, the value of gate to substrate capacitance is equal to:

In Cut-off Mode, the capacitance Cgs will be equal to:

The capacitance that exist between Gate and Bulk is called as:

The parasitic capacitances found in MOSFET are:

The capacitances in MOSFET occurs due to: