What does ECL stand for?

It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.

It stands for electron-coupled logic; all of the devices used within the gates are N-type transistors.

It stands for emitter-coupled logic; all of the inputs are coupled into the device through the emitters of the input transistors.

It stands for emitter-coupled logic; all of the emitters of the input transistors are connected together and each transistor functions as an emitter follower.

It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.

An open-collector TTL gate ________.

can source current but cannot sink current

can sink current but cannot source current

can sink more current than a standard TTL gate

P-MOS and N-MOS ________.

are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate

are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers

A logic probe is placed on the input of a digital circuit and the probe lamp blinks slowly, indicating ________.

that an open or bad logic level exists

A logic probe is placed on the output of a digital circuit and the probe lamp is dimly lit. This display indicates ________.

that an open or bad logic level exists

When the output of a standard TTL gate is HIGH, it can ________.

source 16 mA of current to no more than 10 attached gates

sink 16 mA of current from the attached input gates

source 400 A of current to no more than 10 attached gates

source 16 mA of current to no more than 10 attached gates

sink a maximum of 400 A from no more than 10 load gates

Which of the following statements apply to CMOS devices?

The devices should not be inserted into circuits with the power on.

All tools, test equipment, and metal workbenches should be tied to earth ground.

The devices should be stored and shipped in antistatic tubes or conductive foam.

Refer to the figure given below. What type of device is shown and what input levels are required to turn the LED off?

The device is a Schottky AND gate and requires only one low input to turn the LED off.

The device is an open-collector AND gate and requires both inputs to be HIGH in order to turn the LED off.

The device is a Schottky AND gate and requires only one low input to turn the LED off.

The device is an open-collector AND gate and requires only one low input to turn the LED off.

The device is a Schottky open-collector AND gate and requires a low on both inputs to turn the LED off.

What causes low-power Schottky TTL to use less power than the 74XX series TTL?

The Schottky-clamped transistor

Nothing. The 74XX series uses less power.

What type of circuit is shown below and which statement best describes its operation?

It is a hybrid TTL-CMOS inverter with FET totem-pole output.

It is a two-input CMOS AND gate with open drain.

It is a two-input CMOS buffer with tristate output.

It is a CMOS inverter with tristate output.

It is a hybrid TTL-CMOS inverter with FET totem-pole output.

89 + Mcqs in Integrated Circuit Logic Families in Digital Electronics Page 1 McqOptions

1.	What does ECL stand for?
A.	It stands for electron-coupled logic; all of the devices used within the gates are N-type transistors.
B.	It stands for emitter-coupled logic; all of the inputs are coupled into the device through the emitters of the input transistors.
C.	It stands for emitter-coupled logic; all of the emitters of the input transistors are connected together and each transistor functions as an emitter follower.
D.	It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.
Answer» D. It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.

Discussion

2.	What type of logic circuit is shown below and what logic function is being performed?
A.	It is an NMOS AND gate.
B.	It is a CMOS AND gate.
C.	It is a CMOS NOR gate.
D.	It is a PMOS NAND gate.
Answer» D. It is a PMOS NAND gate.

Discussion

3.	Usually P-MOS and N-MOS circuits are identical with the exception of the voltage polarities.
A.	1
B.
Answer» B.

Discussion

4.	An open-collector TTL gate ________.
A.	can source current but cannot sink current
B.	can sink current but cannot source current
C.	cannot source or sink current
D.	can sink more current than a standard TTL gate
Answer» C. cannot source or sink current

Discussion

5.	P-MOS and N-MOS ________.
A.	represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
B.	are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
C.	represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers
D.	None of the above are.
Answer» B. are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

Discussion

6.	Integrated injection logic offers high component density and is easier to fabricate than TTL.
A.	1
B.
Answer» B.

Discussion

7.	The output current capability for a HIGH output condition is called a source current.
A.	1
B.
Answer» B.

Discussion

8.	Most TTL gates use the totem-pole output arrangement.
A.	1
B.
Answer» B.

Discussion

9.	One advantage that MOSFET transistors have over bipolar transistors is ________.
A.	high input impedance
B.	higher switching speed
C.	low input impedance
D.	reduced propagation delay
Answer» B. higher switching speed

Discussion

10.	When VGS = 0 on an N-channel MOSFET switch, there is no ________ between the source and the drain.
A.	voltage drop
B.	conductive channel
C.	capacitance
D.	inductance
Answer» C. capacitance

Discussion

11.	The lower transistor of a totem-pole output is saturated when the gate output is ________.
A.	overdriven
B.	HIGH
C.	LOW
D.	malfunctioning
Answer» D. malfunctioning

Discussion

12.	A logic probe is placed on the input of a digital circuit and the probe lamp blinks slowly, indicating ________.
A.	that an open or bad logic level exists
B.	a high level output
C.	a high-frequency pulse train
D.	that the supply voltage is low
Answer» D. that the supply voltage is low

Discussion

13.	A common means for measuring and comparing the overall performance of an IC family is the speed-power product.
A.	1
B.
Answer» B.

Discussion

14.	Power-supply decoupling uses a radio-frequency capacitor to short out high frequency spikes.
A.	1
B.
Answer» B.

Discussion

15.	The time it takes for a square wave to go from 10% to 90% of its voltage level is called propagation delay.
A.	1
B.
Answer» C.

Discussion

16.	ECL gates are noted for their high frequency capability and small output voltage swing.
A.	1
B.
Answer» B.

Discussion

17.	________ is ideally suited for applications using battery power or battery backup power.
A.	MOS
B.	P-MOS
C.	N-MOS
D.	CMOS
Answer» E.

Discussion

18.	The maximum current for a LOW output on a standard TTL gate is 100 A.
A.	1
B.
Answer» C.

Discussion

19.	A current-sourcing transistor may also be referred to as a pull-down transistor.
A.	1
B.
Answer» C.

Discussion

20.	A logic probe is placed on the output of a digital circuit and the probe lamp is dimly lit. This display indicates ________.
A.	that an open or bad logic level exists
B.	a high level output
C.	a high-frequency pulse train
D.	that the supply voltage is low
Answer» B. a high level output

Discussion

21.	The logic family with the highest maximum clock frequency is HS-TTL.
A.	1
B.
Answer» C.

Discussion

22.	When the output of a standard TTL gate is HIGH, it can ________.
A.	sink 16 mA of current from the attached input gates
B.	source 400 A of current to no more than 10 attached gates
C.	source 16 mA of current to no more than 10 attached gates
D.	sink a maximum of 400 A from no more than 10 load gates
Answer» C. source 16 mA of current to no more than 10 attached gates

Discussion

23.	When the outputs of several standard TTL gates are connected together, the gate outputs produce more fan-out.
A.	1
B.
Answer» C.

Discussion

24.	Due to the extremely low power requirements of CMOS logic circuits, any number of CMOS and TTL gates can be interconnected.
A.	1
B.
Answer» C.

Discussion

25.	The output stage of a TTL gate is a special design called ________.
A.	multiemitter
B.	totem-pole
C.	MSI
D.	DIP
Answer» C. MSI

Discussion

26.	________ is about twice as fast as P-MOS.
A.	CMOS
B.	DMOS
C.	MOD
D.	N-MOS
Answer» E.

Discussion

27.	The upper transistor of a totem-pole output is OFF when the gate output is low.
A.	1
B.
Answer» B.

Discussion

28.	The proliferation of small handheld consumer equipment such as digital video cameras, cellular phones, handheld computers (________), portable audio systems, and other devices has created a need for logic circuits in very small packages.
A.	HDLs
B.	GDAs
C.	PDAs
D.	TTLs
Answer» D. TTLs

Discussion

29.	Fan-out for a typical TTL gate is ________.
A.	100
B.	54
C.	10
D.	4
Answer» D. 4

Discussion

30.	The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as ________.
A.	fan-out
B.	propagation delay
C.	rise time
D.	fall time
Answer» C. rise time

Discussion

31.	The 74XX series TTL operates using saturated switching in which many of the transistors, when conducting, will be in the saturated condition.
A.	1
B.
Answer» B.

Discussion

32.	The CMOS series that is pin-compatible with the TTL family is the 4000 series.
A.	1
B.
Answer» C.

Discussion

33.	The fan-out of CMOS gates is frequency dependent.
A.	1
B.
Answer» B.

Discussion

34.	________ TTL allows three possible output states.
A.	Triswitch
B.	Triinput
C.	Tristate
D.	Trident
Answer» D. Trident

Discussion

35.	The maximum output voltage recognized as a LOW by a TTL gate is 2.0 V.
A.	1
B.
Answer» C.

Discussion

36.	CMOS stands for "complementary metal-oxide semiconductors" and the FETs are normally enhancement mode devices.
A.	1
B.
Answer» B.

Discussion

37.	In a DIP the spacing between pins is typically ________.
A.	5 mils
B.	10 mils
C.	50 mils
D.	100 mils
Answer» E.

Discussion

38.	The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called ________.
A.	fan-out
B.	propagation
C.	dissipation
D.	SSI
Answer» B. propagation

Discussion

39.	The power dissipation of a CMOS IC will ________.
A.	decrease with frequency
B.	increase with gate size
C.	decrease with gate size
D.	increase with frequency
Answer» E.

Discussion

40.	The HIGH logic level for a standard TTL output must be at least ________.
A.	2.4 V
B.	2 V
C.	0.8 V
D.	5 V
Answer» B. 2 V

Discussion

41.	The major advantage of CMOS logic circuits over TTL is very low power consumption.
A.	1
B.
Answer» B.

Discussion

42.	The ________ is defined as the maximum number of standard logic inputs that an output can drive reliably.
A.	fan-drive
B.	fan-out
C.	fan-in
D.	open-collector
Answer» C. fan-in

Discussion

43.	Which of the following statements apply to CMOS devices?
A.	The devices should not be inserted into circuits with the power on.
B.	All tools, test equipment, and metal workbenches should be tied to earth ground.
C.	The devices should be stored and shipped in antistatic tubes or conductive foam.
D.	All of the above.
Answer» E.

Discussion

44.	An unused input of a NAND gate can be left unconnected, pulled high by a pull-up resistor and tied together with another input and not change the logic output.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

45.	Refer to the given figure. What type of output arrangement is being used for the output?
A.	Complementary-symmetry
B.	Push-pull
C.	Quasi push-pull
D.	Totem-pole
Answer» E.

Discussion

46.	Refer to the figure given below. What type of device is shown and what input levels are required to turn the LED off?
A.	The device is an open-collector AND gate and requires both inputs to be HIGH in order to turn the LED off.
B.	The device is a Schottky AND gate and requires only one low input to turn the LED off.
C.	The device is an open-collector AND gate and requires only one low input to turn the LED off.
D.	The device is a Schottky open-collector AND gate and requires a low on both inputs to turn the LED off.
Answer» B. The device is a Schottky AND gate and requires only one low input to turn the LED off.

Discussion

47.	The 74F-Fast TTL integrated-circuit fabrication technique uses reduced interdevice ________ to achieve reduced propagation delays.
A.	noise
B.	resistance
C.	capacitance
D.	inductance
Answer» D. inductance

Discussion

48.	The propagation delay of standard TTL gates is approximately ________.
A.	2 s
B.	1 s
C.	4 ns
D.	10 ns
Answer» E.

Discussion

49.	What causes low-power Schottky TTL to use less power than the 74XX series TTL?
A.	The Schottky-clamped transistor
B.	Nothing. The 74XX series uses less power.
C.	A larger value resistor
D.	Using NAND gates
Answer» D. Using NAND gates

Discussion

50.	What type of circuit is shown below and which statement best describes its operation?
A.	It is a two-input CMOS AND gate with open drain.
B.	It is a two-input CMOS buffer with tristate output.
C.	It is a CMOS inverter with tristate output.
D.	It is a hybrid TTL-CMOS inverter with FET totem-pole output.
Answer» D. It is a hybrid TTL-CMOS inverter with FET totem-pole output.

Discussion

Explore topic-wise MCQs in Digital Electronics.

What does ECL stand for?

What type of logic circuit is shown below and what logic function is being performed?

Usually P-MOS and N-MOS circuits are identical with the exception of the voltage polarities.

An open-collector TTL gate ________.

P-MOS and N-MOS ________.

Integrated injection logic offers high component density and is easier to fabricate than TTL.

The output current capability for a HIGH output condition is called a source current.

Most TTL gates use the totem-pole output arrangement.

One advantage that MOSFET transistors have over bipolar transistors is ________.

When VGS = 0 on an N-channel MOSFET switch, there is no ________ between the source and the drain.

The lower transistor of a totem-pole output is saturated when the gate output is ________.

A logic probe is placed on the input of a digital circuit and the probe lamp blinks slowly, indicating ________.

A common means for measuring and comparing the overall performance of an IC family is the speed-power product.

Power-supply decoupling uses a radio-frequency capacitor to short out high frequency spikes.

The time it takes for a square wave to go from 10% to 90% of its voltage level is called propagation delay.

ECL gates are noted for their high frequency capability and small output voltage swing.

________ is ideally suited for applications using battery power or battery backup power.

The maximum current for a LOW output on a standard TTL gate is 100 A.

A current-sourcing transistor may also be referred to as a pull-down transistor.

A logic probe is placed on the output of a digital circuit and the probe lamp is dimly lit. This display indicates ________.

The logic family with the highest maximum clock frequency is HS-TTL.

When the output of a standard TTL gate is HIGH, it can ________.

When the outputs of several standard TTL gates are connected together, the gate outputs produce more fan-out.

Due to the extremely low power requirements of CMOS logic circuits, any number of CMOS and TTL gates can be interconnected.

The output stage of a TTL gate is a special design called ________.

________ is about twice as fast as P-MOS.

The upper transistor of a totem-pole output is OFF when the gate output is low.

The proliferation of small handheld consumer equipment such as digital video cameras, cellular phones, handheld computers (________), portable audio systems, and other devices has created a need for logic circuits in very small packages.

Fan-out for a typical TTL gate is ________.

The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as ________.

The 74XX series TTL operates using saturated switching in which many of the transistors, when conducting, will be in the saturated condition.

The CMOS series that is pin-compatible with the TTL family is the 4000 series.

The fan-out of CMOS gates is frequency dependent.

________ TTL allows three possible output states.

The maximum output voltage recognized as a LOW by a TTL gate is 2.0 V.

CMOS stands for "complementary metal-oxide semiconductors" and the FETs are normally enhancement mode devices.

In a DIP the spacing between pins is typically ________.

The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called ________.

The power dissipation of a CMOS IC will ________.

The HIGH logic level for a standard TTL output must be at least ________.

The major advantage of CMOS logic circuits over TTL is very low power consumption.

The ________ is defined as the maximum number of standard logic inputs that an output can drive reliably.

Which of the following statements apply to CMOS devices?

An unused input of a NAND gate can be left unconnected, pulled high by a pull-up resistor and tied together with another input and not change the logic output.

Refer to the given figure. What type of output arrangement is being used for the output?

Refer to the figure given below. What type of device is shown and what input levels are required to turn the LED off?

The 74F-Fast TTL integrated-circuit fabrication technique uses reduced interdevice ________ to achieve reduced propagation delays.

The propagation delay of standard TTL gates is approximately ________.

What causes low-power Schottky TTL to use less power than the 74XX series TTL?

What type of circuit is shown below and which statement best describes its operation?