

MCQOPTIONS
This section includes 30 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
1. |
The hexadecimal number (3E8)16 is equal to decimal number |
A. | 1000 |
B. | 982 |
C. | 768 |
D. | 323 |
Answer» B. 982 | |
2. |
The expression Y = pM (0, 1, 3, 4) is |
A. | POS |
B. | SOP |
C. | Hybrid |
D. | none of the above |
Answer» B. SOP | |
3. |
Find the output voltage for 011100 in a 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. |
A. | 6.4 V |
B. | 2.84 V |
C. | 0.1 V |
D. | 8 V |
Answer» C. 0.1 V | |
4. |
Assertion (A): The output of a NOR gate is equal to the complement of OR of input variables. Reason (R): A XOR gate is a universal gate. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
5. |
Assertion (A): A demultiplexer can be used as a decoder. Reason (R): A demultiplexer can be built by using AND gates only. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
6. |
For a MOD-12 counter, the FF has a tpd = 60 ns The NAND gate has a tpd of 25 n sec. The clock frequency is |
A. | 3.774 MHz |
B. | > 3.774 MHz |
C. | < 3.774 MHz |
D. | 4.167 MHz |
Answer» B. > 3.774 MHz | |
7. |
In a D latch |
A. | data bit D is fed to S input and D to R input |
B. | data bit D is fed to R input and D to S input |
C. | data bit D is fed to both R and S inputs |
D. | data bit D is not fed to any input |
Answer» B. data bit D is fed to R input and D to S input | |
8. |
In a 7 segment display, LEDs b and c lit up. The decimal number displayed is |
A. | 9 |
B. | 7 |
C. | 3 |
D. | 1 |
Answer» E. | |
9. |
If the inputs to a 3 bit binary adder are 1112 and 1112, the output will be 110. |
A. | True |
B. | False |
Answer» C. | |
10. |
Assertion (A): TTL is a very popular logic in SSI and MSI category. Reason (R): In Schottky TTL the power dissipation is less than in ordinary TTL. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
11. |
Assertion (A): ECL gate has very high speed of operation. Reason (R): Transistors in ECL do not go into saturation region. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» B. Both A and R are correct but R is not correct explanation of A | |
12. |
Assertion (A): Tristate logic is used for bus oriented systems Reason (R): The outputs of a tristate logic are 0, 1 and indeterminant. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
13. |
Assertion (A): CMOS devices have very high speed. Reason (R): CMOS devices have very small physical size and simple geometry. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» E. | |
14. |
Find the FSV (full scale voltage) in a 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. |
A. | 6.4 V |
B. | 0.1 V |
C. | 7 V |
D. | 8 V |
Answer» B. 0.1 V | |
15. |
Assertion (A): A multiplexer can be used for data routing. Reason (R): A multiplexer has one input and many outputs. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
16. |
Assertion (A): Synchronous counter has higher speed of operation than ripple counter Reason (R): Synchronous counter uses high speed flip flops. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
17. |
Assertion (A): ECL is fast as compared to TTL. Reason (R): ECL dissipates less power than TTL. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» D. A is false, R is true | |
18. |
The applications of shift registers are 1.Time delay 2.Ring counter 3.Serial to parallel data conversion 4.Serial to serial data conversion Which of the above are correct? |
A. | 1, 2, 3 |
B. | 2, 3, 4 |
C. | 1, 2, 3, 4 |
D. | 1, 2, 4 |
Answer» D. 1, 2, 4 | |
19. |
A 2 bit BCD D/A converter is a weighted resistor type with ER = 1V, R = 1 M and Rf = 10K then Resolution in percent and volt is __________ . |
A. | 1%, 1 mv |
B. | 10%, 10 mv |
C. | 10%, 1 mv |
D. | 1%, 10 mv |
Answer» E. | |
20. |
Assertion (A): XOR gate is not universal gate. Reason (R): It is not possible to realize any Boolean function using XOR gates only. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» B. Both A and R are correct but R is not correct explanation of A | |
21. |
Assertion (A): In computers the data is stored in hexadecimal form Reason (R): Hexadecimal representation is short as compared to binary representation. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» E. | |
22. |
In a 7 segment display the segments a, c, d, f, g are lit. The decimal number displayed will be |
A. | 9 |
B. | 5 |
C. | 4 |
D. | 2 |
Answer» C. 4 | |
23. |
The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is |
A. | 8 |
B. | 9 |
C. | 10 |
D. | 11 |
Answer» D. 11 | |
24. |
A 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. It meets standard linearity then resolution in percent and volts. |
A. | 3% 7 V |
B. | 6.4 V, 2% |
C. | 0.1%, 1.57 V |
D. | 1.57%, 0.1 V |
Answer» E. | |
25. |
What will be conversion rate for a counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time |
A. | 125 |
B. | 125 x 103 |
C. | 125 x 106 |
D. | None |
Answer» E. | |
26. |
Which of the following characteristic are necessary for a sequential circuit? 1.It must have 6 gates 2.It must have feedback 3.Its output should depend on past value Which of the above statements are correct? |
A. | 1, 2, 3 |
B. | 1, 2 |
C. | 2, 3 |
D. | 1, 3 |
Answer» D. 1, 3 | |
27. |
Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is needed to interconnect them Reason (R): VOH, VOL, VIH and VIL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V. VIL and VIH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» B. Both A and R are correct but R is not correct explanation of A | |
28. |
In a 4 bit ripple counter using flip flops with tpd = 40 ns, the maximum frequency can be |
A. | 1.25 MHz |
B. | 3.25 MHz |
C. | 6.25 MHz |
D. | 12.5 MHz |
Answer» D. 12.5 MHz | |
29. |
Assertion (A): A PROM can be used as a synchronous counter Reason (R): Each memory location in a PROM can be read synchronously. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» E. | |
30. |
Assertion (A): The access time of memory is lowest in the case of DRAM Reason (R): DRAM uses refreshing cycle. |
A. | Both A and R are correct and R is correct explanation of A |
B. | Both A and R are correct but R is not correct explanation of A |
C. | A is true, R is false |
D. | A is false, R is true |
Answer» E. | |