The advantage of a J-K flip-flop over an S-R FF is that ________.

it does not require a clock input

A gated S-R flip-flop is in the hold condition whenever ________.

the S and R inputs are both LOW

the Gate Enable is HIGH and the S and R inputs are both LOW

What type of multivibrator is a latch?

It depends on the type of latch.

An edge-triggered flip-flop can change states only when ________.

the trigger input changes levels

The asynchronous inputs on a J-K flip-flop ________.

are normally not at the active level at the same time

take precedence over the J and K inputs

do not require a clock pulse to affect the output

Setup time specifies ________.

the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF

the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF

the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF

how long the operator has in order to get the flip-flop running before the maximum power level is exceeded

how long it takes the output to change states after the clock has transitioned

The signal used to identify edge-triggered flip-flops is ________.

the letter "E" on the enable input

161 + Mcqs in Flip Flops in Digital Electronics Page 1 McqOptions

1.	An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» B. [B].

2.	Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
A.	[A].
B.	[B].
C.	[C].
D.	[D].
Answer» E.

3.	A flip-flop operation is described as a toggle when the result after a clock is ________.
A.	[A].
B.	[B].
C.	[C].
D.	change to opposite states
Answer» E.

4.	The term hold always means ________.
A.	[A].
B.	[B].
C.	[C].
D.	no change
Answer» E.

5.	A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.
A.	3
B.	7
C.	10
D.	13
Answer» E.

6.	ICs can perform sequential operations, including counting and data shifting.
A.	1
B.
Answer» B.

7.	The major advantage of a Schmitt trigger input is that it ________.
A.	avoids erratic triggering
B.	has more triggering methods
C.	has a wider range of outputs
D.	can be retriggered
Answer» B. has more triggering methods

8.	The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.
A.	point 4
B.	points 3 and 4
C.	points 1 and 2
D.	points 4 and 5
Answer» B. points 3 and 4

9.	The advantage of a J-K flip-flop over an S-R FF is that ________.
A.	it has fewer gates
B.	it has only one output
C.	it has no invalid states
D.	it does not require a clock input
Answer» D. it does not require a clock input

10.	The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.
A.	1
B.
Answer» C.

11.	Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.
A.	1
B.
Answer» C.

12.	Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.
A.	PROCESS
B.	computer
C.	simulator
D.	primitive library
Answer» D. primitive library

14.	The action of ________ a FF or latch is also called resetting.
A.	breaking
B.	clearing
C.	freeing
D.	changing
Answer» C. freeing

15.	A latch can act as a contact-bounce eliminator.
A.	1
B.
Answer» B.

17.	A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.
A.	1
B.
Answer» C.

13.	A gated S-R flip-flop is in the hold condition whenever ________.
A.	the Gate Enable is HIGH
B.	the Gate Enable is LOW
C.	the S and R inputs are both LOW
D.	the Gate Enable is HIGH and the S and R inputs are both LOW
Answer» E.

16.	The S-R flip-flop has no invalid or unused state.
A.	1
B.
Answer» C.

18.	The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.
A.	logic level
B.	flip-flop
C.	edge-detector circuit
D.	toggle detector
Answer» C. edge-detector circuit

19.	The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.
A.	1
B.
Answer» B.

20.	A flip-flop is in the CLEAR condition when .
A.	1
B.
Answer» C.

21.	What type of multivibrator is a latch?
A.	Astable
B.	Monostable
C.	Bistable
D.	It depends on the type of latch.
Answer» D. It depends on the type of latch.

22.	An edge-triggered flip-flop can change states only when ________.
A.	the trigger is HIGH
B.	the D input is HIGH
C.	the trigger is LOW
D.	the trigger input changes levels
Answer» E.

23.	The 7476 and 74LS76 are both dual flip-flops.
A.	1
B.
Answer» B.

24.	The postponed symbol () on the output of a flip-flop identifies it as being ________.
A.	a D flip-flop
B.	a J-K flip-flop
C.	pulse triggered
D.	trailing edge-triggered
Answer» D. trailing edge-triggered

25.	Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.
A.	1
B.
Answer» B.

Explore topic-wise MCQs in Digital Electronics.

An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

A flip-flop operation is described as a toggle when the result after a clock is ________.

The term hold always means ________.

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

ICs can perform sequential operations, including counting and data shifting.

The major advantage of a Schmitt trigger input is that it ________.

The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.

The advantage of a J-K flip-flop over an S-R FF is that ________.

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.

Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.

Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.

A gated S-R flip-flop is in the hold condition whenever ________.

The action of ________ a FF or latch is also called resetting.

A latch can act as a contact-bounce eliminator.

The S-R flip-flop has no invalid or unused state.

A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

A flip-flop is in the CLEAR condition when .

What type of multivibrator is a latch?

An edge-triggered flip-flop can change states only when ________.

The 7476 and 74LS76 are both dual flip-flops.

The postponed symbol () on the output of a flip-flop identifies it as being ________.

Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.

Connecting components together using HDL is not difficult.

The 7474 has two distinct types of inputs: synchronous and asynchronous.

Latches are tristate devices whose state normally depends on asynchronous inputs.

Edge-triggered flip-flops can be identified by the triangle on the clock input.

A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.

In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.

A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

A major drawback to an latch is its ________.

An astable multivibrator is sometimes referred to as a clock.

A J-K flip-flop and associated waveforms are shown below. The circuit is operating properly.

The asynchronous inputs on a J-K flip-flop ________.

Setup time specifies ________.

The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.

When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:

The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.

Multivibrators must be level-triggered.

Some flip-flops have invalid states.

A one-shot circuit is also known as a timer.

The 555 timer can be used in either the astable or monostable modes.

Parallel data transfers between two different sets of registers require more than one shift pulse.

Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.

The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.

The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.

The signal used to identify edge-triggered flip-flops is ________.

32.	In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
A.	function
B.	signal
C.	semicolon
D.	colon
Answer» E.

34.	A major drawback to an latch is its ________.
A.	complexity
B.	slow speed
C.	invalid condition
D.	latch mode
Answer» D. latch mode

39.	The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.
A.	one resistor
B.	two resistors
C.	one capacitor
D.	a resistor and a capacitor
Answer» E.

40.	When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:
A.	S = 1, R = 1
B.	S = 1, R = 0
C.	S = 0, R = 1
D.	S = 0, R = 0
Answer» D. S = 0, R = 0

48.	The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.
A.	capacitor
B.	inductor
C.	resistor
D.	LED
Answer» B. inductor

49.	The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.
A.	Only S
B.	S and R
C.	Only D
D.	All of the above.
Answer» E.

50.	The signal used to identify edge-triggered flip-flops is ________.
A.	a bubble on the clock input
B.	an inverted "L" on the output
C.	the letter "E" on the enable input
D.	a triangle on the clock input
Answer» E.